Static random access memory allowing reading angle rotation

Claim 1

A static random access memory, comprising: plurality of memory cells arranged in a plurality of rows and columns; a plurality of first word lines provided corresponding to said plurality of rows, each connected to memory cells of the corresponding row; plurality of second word lines provided corresponding to said plurality of columns, each connected to memory cells of the corresponding column;. a plurality of first single bit lines provided corresponding to said plurality columns, each connected to memory cells of the corresponding column; a plurality of second single bit lines provided corresponding to said plurality of columns, each connected to memory cells of the corresponding row; first word selecting means for selecting any of said plurality of first word lines; second word selecting means for selecting any of said plurality of second word lines; first bit selecting means for selecting any of said plurality of first single lines; second bit selecting means for selecting any of said plurality of second bit lines; writing means for writing data to a single bit line selected by said first bit selecting means in writing operation; and reading means for reading data of a single bit line selected by said first or second bit selecting means; wherein each of said plurality of memory cells includes first and second nodes to which complementary data are applied, holding means for holding complementary data of said first and second node, first single access gate means connected between said first node and the corresponding first single bit line and having a control terminal connected to the corresponding first word line, and second single access gate means connected between said second node and the corresponding second single bit line and having a control terminal connected to the corresponding second word line, wherein said writing means includes at least one writing means connected to at least one of said first and second bit selecting means, and said reading means includes first reading means connected to said first bit selecting means and second reading means connected to said second bit selecting means, said memory further comprising: a data output terminal and switching means for selectively connecting one of said first and second reading means to said data output terminal.