Memory architecture

Claim 2

Memory architecture device for providing equally fast access to stored data in two or more dimensions including an n x m matrix array of bit storage cells having n rows and m columns; characterized by a plurality of dimension word lines (WL I) for accessing said rows of said cells (20) in the array (50), with each of said dimension word lines being connected to a corresponding one of said rows of the cells, by a plurality of dimension word lines (WL II) for accessing said columns of said cells (20) in said array (50), with each of said dimension word lines being connected to a corresponding one of said columns of said cells, with the dimension word lines (WL I) being orthogonal to the dimension word lines (WL II), and with each of the cells being connected to only a single corresponding one of the dimension word lines (WL I) and to only a single corresponding one of the dimension word lines (WL II); by a plurality of dimension bit lines (BL I) for detecting the state of said cells in said rows of the array, with each of said dimension bit lines (BL II) being connected to a corresponding one of said rows of the cells of the array; and by a plurality of dimension bit lines (BL I) for detecting the state of said cells in columns of the array, with each of said dimension bit lines (BL I) being connected to a corresponding one of columns of the cells of the array, with the dimension bit lines (BL I) being orthogonal to the dimension bit lines (BL II), and with each of the cells (20) being connected to only a single corresponding one of said dimension bit lines (BL II) and only a single corresponding one of said dimension bit lines (BL I), whereby the state of a selected one of the storage cells (20) can be detected from either of two orthogonal directions by accessing the selected cell with one of said dimension word lines (WL I) connected to said selected cell or one of the dimension word lines (WL II) connected to the selected cell, and by detecting the state of the selected cell by reading the voltage on one of the dimension bit lines (BL II) connected to the selected cell if said selected cell is accessed with one of the dimension word lines (WL II) connected to the selected cell, or on one of the dimension bit lines (BL I) connected to the selected cell if the selected cell is accessed with one of said dimension word lines (WL I) connected to the selected cell, and whereby the state of the selected cell can be changed by accessing said selected cell in either one of two directions, and then subsequently accessing said selected cell in the other of said two directions, wherein the state of said selected cell will change according to the voltage on the bit lines.

Claim 3

Memory architecture as recited in claim 1, characterized in that each of the cells comprises at most two access devices (TA 1, 2) and a latch (T1 - T4), there being at most one access device for each direction of access.

Claim 4

Memory architecture as recited in claim 2, characterized in that each access device has a smaller current carrying capability than any device of a flip-flop so as to provide a stable read.

Claim 5

Memory architecture as recited in claim 1, characterized by means for decoding at least one dimension bit so as to enable one of said word line decoders (52 or 54) which corresponds to the dimension indicated by said dimension bit whereby one decoder decodes the address so as to access said selected cell in the direction indicated by said dimension bit.

Claim 6

Memory architecture as set forth in claim 1, characterized by an N x M matrix of cell arrays (TMA) having N rows and M columns, each i-th one of said arrays being an n i x m i array of bit storage cells; by a plurality of dimension I word line decoders (52) with each one of the cell arrays (TMA) having an associated one of said dimension I word line decoders (52); by a plurality of dimension II word line decoders (54) with each one of said cell arrays having an associated one of said dimension II word line decoders (54); by a plurality of dimension II bit line decoders (56) with each one of said cell arrays having an associated one of said dimension II bit line decoders (56); by a plurality of dimension I bit line decoders (58) with each one of said cell arrays having an associated one of said dimension I bit line decoders (58); by a plurality of dimension I word lines with each i-th of said dimension I word line decoders being used to place a high or a low voltage on selected ones of a set of n i dimension I word lines, each of said dimension I word lines being used to access a corresponding row of said bit storage cells in a corresponding one of said cell arrays (TMA); by a plurality of dimension II word lines with each i-th of said dimension II word line decoders being used to place a high or a low voltage on selected ones of a set of m i of said dimension II word lines, each of said dimension II word lines being used to access a corresponding column of said bit storage cells in a corresponding one of said cell arrays (TMA); by a plurality of dimension II bit lines, with each i-th of said dimension II bit line decoders being used to select a subset in a set of n i of said dimension II bit lines, each of said dimension II bit lines in said subset being used to detect or establish the state of a first of said bit storage cells in a corresponding row of said cells in said i-th of said cell arrays (TMA), said first cell being a cell which has been accessed by a dimension II word line corresponding to the column in which said first cell is located; and by a plurality of dimension I bit lines, with each i-th of said dimension I bit line decoders being used to select a subset in a set of m i of said dimension I bit lines, each of said dimension I bit lines in said subset of being used to detect or establish the state of a second of said bit storage cells in a corresponding column of said cells in said i-th of said cell arrays (TMA), said second cell being a cell which has been accessed by a dimension I word line (of said dimension I word lines) corresponding to the row in which said second cell is located, whereby at least one of said cells from each of said arrays may be accessed at the same time and in the same manner as described in steps for said i-th array.

Claim 7

Memory architecture device for reading or writing a data unit stored in said device, wherein said data unit may extend in one of a multiple of mutually orthogonal direction, as set forth in claim 1 or 5, characterized by an N x M matrix of cell arrays (TMA) having N rows and M columns, each i-th one of said arrays being an n i x m i array (50) of bit storage cells, by a plurality of dimension I word line decoders (52) with each one of said cell arrays having an associated one of said dimension I word line decoders, by a plurality of dimension II word line decoders (54) with each one of said cell arrays having an associated one of said dimension II word line decoders, by a plurality of dimension II bit line decoders (56) with each one of said cell arrays having an associated one of said dimension II bit line decoders, by a plurality of dimension I bit line decoders (58) with each one of said TMA cell arrays having an associated one of said dimension I bit line decoders, by a plurality of dimension I word lines with each i-th of said dimension I word line decoders being used to place a high or low voltage on selected ones of a set of n i of said dimension I word lines, each of said dimension I word lines being used to access a corresponding row of said bit storage cells in a corresponding one of the cell arrays (TMA); by a plurality of dimension II word lines with each i-th of said dimension II word line decoders being used to place a high or low voltage on selected ones of a set of mi of said dimension II word lines, each of said dimension II word lines being used to access a corresponding column of said bit storage cells in a corresponding one of the cell arrays (TMA); by a plurality of dimension II bit lines, with each i-th of said dimension II bit line decoders being used to select a first subset in a set of n i of said dimension II bit lines, each of said dimension II bit lines in said firs subset being used to detect or establish the state of said bit storage cells in a corresponding row of said cells in said i-th of said cell arrays, each cell which has been accessed and which is of said corresponding row of said i-th cell array (TMA) being a cell which has been accessed by a dimension II word line corresponding to the column in which that cell is located; by a plurality of dimension I bit lines, with each i-th of said dimension I bit line decoders being used to select a second subset in a set of m i of said dimension I bit lines each of said dimension I bit lines in said second subset being used to detect or establish the state of said bit storage cells in a corresponding column of said cells in a corresponding one of said cell arrays, each cell which has been accessed and which is of said corresponding column of the i-th cell array (TMA) being a cell which has been accessed by a dimension I word line corresponding to the row in which that cell is located; and by means for decoding a dimension bit so as to enable word and bit line decoders which correspond to a data dimension indicated by a dimension bit, said word and bit line decoders being said dimension I word line decoder and said dimension I bit line decoder, or said dimension II word line decoder and said dimension I bit line decoder depending on whether said dimension bit indicates a dimension I data direction or a dimension II data direction.