Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
184 words
Highly integrated multi-port static random access memory (SRAM) comprising asymmetrical CMOS flip-flops (FF) as storage cells, further comprising a plurality of intersection bit and word lines forming crosspoints therebetween, a plurality of storage locations provided at the crosspoints and connected to the respective bit and word lines for selecting a single bit group, particularly a single byte for a fast write or write-through operation, characterized by dividing the cell matrix in i blocks of k bit columns each (k = 1, 2, ...); by a column of AND gates (A) connected to every block, the AND gates linking the block word lines (WLw) to the respective main write word lines (WL) depending on the state of a unique write byte control signal (WBi); by a cross-coupled inverter pair (T2, T3; T4, T5) forming the asymmetrical CMOS flip-flop (FF), where the first flip-flop inverter (T2, T3) is designed to drive attached inverter buffers or preamplifiers, and the second flip-flop inverter (T4, T5) contains a minimum-width and long-channel N field effect transistor (NFET) to reduce the countereffect when writing a high-level through the write port (NFET).
Claim 2
Dependent Claim
184 words
Highly integrated multi-port static random access memory (SRAM) comprising asymmetrical CMOS flip-flops (FF) as storage cells, further comprising a plurality of intersection bit and word lines forming crosspoints therebetween, a plurality of storage locations provided at the crosspoints and connected to the respective bit and word lines for selecting a single bit group, particularly a single byte for a fast write or write-through operation, characterized by dividing the cell matrix in i blocks of k bit columns each (k = 1, 2, ...); by a column of AND gates (A) connected to every block, the AND gates linking the block word lines (WLw) to the respective main write word lines (WL) depending on the state of a unique write byte control signal (WBi); by a cross-coupled inverter pair (T2, T3; T4, T5) forming the asymmetrical CMOS flip-flop (FF), where the first flip-flop inverter (T2, T3) is designed to drive attached inverter buffers or preamplifiers, and the second flip-flop inverter (T4, T5) contains a minimum-width and long-channel N field effect transistor (NFET) to reduce the countereffect when writing a high-level through the write port (NFET).
Claim 3
Dependent Claim
97 words
Multi-port static random access memory (SRAM) as set forth in claim 1, characterized by activating a byte-write clock signal (WBi) which is fed into a column of the AND gates (A) located at the edge of the block of cells, where one of these AND gates connected to the selected main word line (WL) is enabled to perform the final decoding as soon as the write clock signal (WBi) goes to the signal high level; by gating all write devices of the attached group of cells; by raising the potential on the associated block word line (WLw).
Claim 4
Dependent Claim
51 words
Multi-port static random access memory (SRAM), as set forth in claim 1 or 2, characterized by using a multi-port cell with an asymmetrical flip-flop (FF) and a single device per write port, and by implementing a write-bit group control in the write word line (WL) common to all attached multi-port cells.
Claim 5
Dependent Claim
48 words
Multi-port static random access memory (SRAM) as set forth in any one of claims 1 to 3, characterized in that each multi-port cell contains inverter buffers in the read ports, and in that the single-ended write is accelerated significantly by an asymmetrical flip-flop (FF) with a weak feedback.
Claim 6
Dependent Claim
77 words
Multi-port static random access memory (SRAM) with asymmetrical flip-flops as cells of claims 1 or 4 characterized in that the first inverter (T2, T3) contains devices slightly larger than minimum and adjusted to the device of the attached inverter buffer (T6, T7), and that the second (feedback) inverter contains a minimum-width and long-channel N-channel field effect transistor (T4) to prevent the countereffect when pulling up the flip-flop node (1) by the write N-channel field effect transistor (T1).
Claim 7
Dependent Claim
30 words
Multi-port static random access memory (SRAM), as set forth in any one of claims 1 - 5, characterized in that the bit groups consist of half bytes, bytes or multi-bytes.
Claim 8
Dependent Claim
33 words
Multi-port static random access memory (SRAM) as set forth in any one of the claims 1 to 6, characterized in that the field effect transistors (FETs) of the write ports are P-channel devices.