EP0237813A2
Expired / Lapsed
EP
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Semiconductor memory device having improved precharge scheme
Assignee: NEC Corp
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Filing: 1987-02-17
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Granted: —
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Expires: 2007-02-17
Abstract
Abstract A semiconductor memory device provided with an improved precharge scheme for bit lines is disclosed. A plurality of bit lines are divided into a plurality of bit line group and a precharge control signal is applied only to precharge transistors in a selected bit line group.
Inventors
- 👤 Kenji Kondo
- 👤 Yasuhiko Rai
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 03:41
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419; G11C7/00; G11C7/12; G11C8/00; G11C8/12
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
141 words
A semiconductor memory device comprising a plurality of memory cells arranged in rows and columns, a plurality of word lines arranged in rows, a plurality of bit lines, said bit lines being divided into a plurality of bit line groups, a plurality of precharge transistors provided for said bit lines for operatively precharging said bit lines to a predetermined potential, a row decoder for operatively selecting one of said word lines, a group selection decoder for operatively generating group selection signals for said bit line groups, a timing circuit for operatively generating a first timing signal, a selective precharge control circuit responsive to said group selection signals for operatively rendering the precharge transistors conductive associated to one of said bit line groups in synchronism with said first timing signal thereby to precharge the bit lines of said one bit line group.
Claim 2
Dependent Claim
141 words
A semiconductor memory device comprising a plurality of memory cells arranged in rows and columns, a plurality of word lines arranged in rows, a plurality of bit lines, said bit lines being divided into a plurality of bit line groups, a plurality of precharge transistors provided for said bit lines for operatively precharging said bit lines to a predetermined potential, a row decoder for operatively selecting one of said word lines, a group selection decoder for operatively generating group selection signals for said bit line groups, a timing circuit for operatively generating a first timing signal, a selective precharge control circuit responsive to said group selection signals for operatively rendering the precharge transistors conductive associated to one of said bit line groups in synchronism with said first timing signal thereby to precharge the bit lines of said one bit line group.
Claim 3
Dependent Claim
21 words
The memory device according to Claim 1, in which said row decoder is enabled after said first timing signal is generated.
Claim 4
Dependent Claim
78 words
The memory device according to Claim 1, in which said selective precharge control circuit includes a plurality of gates each provided for each of said bit line groups, each of said gate circuits receiving each one of said group selection signals and said first timing signal, and a plurality of connecting means, each of said connecting means connecting an output of each of said gate circuits and gates of the precharge transistors associated to each bit line group.
Claim 5
Dependent Claim
40 words
The memory device according to Claim 1, further comprising a plurality of bit line selection circuits each provided for each of said bit line groups, each of said bit line selection circuits operatively selecting a bit line or bit lines.
Claim 6
Dependent Claim
94 words
A semiconductor memory device comprising a plurality bit line groups including a plurality of bit lines, a plurality of memory cells, a control circuit for generating a precharge timing signal, a plurality of precharge circuits for said bit lines, a group selection decoder for designating one of said bit line groups, a timing signal generating circuit for operatively generating a precharge timing signal, and a precharge control circuit for operatively energizing the precharge circuits associated only to the bit line group designated by said group selection decoder in synchronism with said precharge timing signal.
Claim 7
Dependent Claim
94 words
A semiconductor memory device comprising a plurality bit line groups including a plurality of bit lines, a plurality of memory cells, a control circuit for generating a precharge timing signal, a plurality of precharge circuits for said bit lines, a group selection decoder for designating one of said bit line groups, a timing signal generating circuit for operatively generating a precharge timing signal, and a precharge control circuit for operatively energizing the precharge circuits associated only to the bit line group designated by said group selection decoder in synchronism with said precharge timing signal.
References Cited (Backward Citations)
No citation records indexed.
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