Time shared interconnection apparatus

Abstract

Abstract AN ARRAY OF ACTUABLE DEVICES EACH REQUIRING TWO INPUTS FOR ACTUATING IS DISCLOSED. DURING A FIRST TIME PERIOD, ONE ROW OF THE ARRAY IS SEPARATELY ACTUABLE VIA COMMON INTERCONNECTIONS TO COLUMNS OF ACTUABLE DEVICES AND A COMMON ROW CONNECTION AND STORES INFORMATION IN BINARY FORM. EACH OF THE DEVICES IN THE ROW IS CONNECTED TO A COLUMN F ACTUABLE DEVICES AND TO AN ACTUABLE GATE WHICH IS ACTUATED OR NOT ACTUATED DEPENDING ON THE STATE OF THE ACTUABLE DEVICES OF THE SEPARATELY CTUATED ROW. EACH GATE IS ALSO CONNECTED TO S SEPARATE ROW OF THE ARRAY. DURING A SECOND TIME PERIOD, THE COLUMNS OF ACTUABLE DEVICES, ARE ACTUATED FROM PULSED SOURCES VIA THEIR COMMON INTERCONNECTION AND FROM IS PULSED SOURCE CONNECTED IN COMMON TO ALL THE GATES. SINCE ONLY ONE GATE CONNECTED TO A ROW IS ACTUATED AND ALL COLUMNS OF DEVICES ARE ACTUATED, ONLY THOSE DEVICES IN THAT ROW ARE ACTUATED. IN A MEMORY ENVIRONMENT, THE FOREGOING OPERATION IS CHARACTERIZED AS WRITING. TO DETECT THE CONDITION OF SELECTED OF THE ACTUATED DEVICES, AN ACTUABLE GATE IS SELECTED DURING A FIRST TIME PERIOD AND, DURING A SECOND TIME PERIOD, SENSING DEVICES ARE CONNECTED TO THE COLUMNS OF ACTUABLE DE- VICES AND, THE COMMON INTERCONNECTION TO A ROW OF ACTUABLE DEVICES IS ACTIVATED FROM A PULSED SOURCE. IN A MEMORY INVIRONMENT, THE FOREGOING OPERATION IS CHARACTERIZED AS READING. THE ACTUABLE DEVICES MAY BE MEMORY CELLS, BISTABLE CIRCUITS OR THE LIKE. THE ARRANGEMENT SHOWN IS PARTICULARLY ADAPTED TO THE SEMICONDUCTOR CHIP ENVIRONMENT WHERE REDUCTION OF INTERCONNECTIONS IS A SIGNIFICANT DESIGN FACTOR. OTHER ARRANGEMENTS SHOWING DECODING ON THE CHIP AND MORE THAN TWO TIME PERIODS ARE ALSO DIS CLOSED.

Inventors

• 👤 Fritz H Gaensslen

Bibliographic Details