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US5418931A Expired / Lapsed US ⏱️ 0.0 years remaining

Method and apparatus for detecting timing errors in digital circuit designs

Assignee: Cadence Design Systems Inc
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Filing: 1994-05-03
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Granted: 1995-05-23
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Expires: 2014-05-03
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Abstract

Abstract Disclosed is a system and method for simulating and detecting timing errors in digital circuit designs. The system consists of a logic simulator connected to various storage registers, a sequencer, and a randomizer, for simulating component functionality within the digital circuit design at sequential time increments using stored parametric data. The method includes selecting, for each component in a digital circuit design, a specific timing constraint from a range of possible timing constraint values, using a psuedo-random selection algorithm. The digital circuit is then simulated through a number of periods using this timing constraint. When an adequate number of periods have been simulated, a new set of timing constraints are selected. Timing requirement violations are detected and reported to a user.

Inventors

  • 👤 Philip R. Moorby

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-07 20:29
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33

Claims Analysis

Total Claims: 8
Claim 1
Independent Claim 246 words
A system for simulating and detecting timing errors in a circuit design that includes electronic components, the system comprising: a net list register for storing a net list of electronic components in a circuit design; a model memory register for storing parametric timing constraint data comprising a minimum and a maximum time delay value for each electronic component in said circuit design; an input value register for storing simulation input values for said circuit design; a sequencer for storing a simulation time period value and for providing notification when the end of said simulation time period is reached; a randomizer for generating and storing a set of delay samples associated with each electronic component as a function of a range defined by said minimum and said maximum time delay values associated with each electronic component, wherein a greater number of delay samples are generated and stored at said minimum and said maximum time delay values than at other delay times within the range; and a logic simulator connected to said net list register, model memory register, input value register, sequencer, and randomizer, for simulating the circuit design in order to detect timing errors, wherein said simulation values are used as inputs to said circuit design and a time delay is chosen for each electronic component from said set of delay samples associated with each electronic component, wherein the time delay chosen for a first component is independent of the time delay chosen for a second component.
Claim 2
Independent Claim 246 words
A system for simulating and detecting timing errors in a circuit design that includes electronic components, the system comprising: a net list register for storing a net list of electronic components in a circuit design; a model memory register for storing parametric timing constraint data comprising a minimum and a maximum time delay value for each electronic component in said circuit design; an input value register for storing simulation input values for said circuit design; a sequencer for storing a simulation time period value and for providing notification when the end of said simulation time period is reached; a randomizer for generating and storing a set of delay samples associated with each electronic component as a function of a range defined by said minimum and said maximum time delay values associated with each electronic component, wherein a greater number of delay samples are generated and stored at said minimum and said maximum time delay values than at other delay times within the range; and a logic simulator connected to said net list register, model memory register, input value register, sequencer, and randomizer, for simulating the circuit design in order to detect timing errors, wherein said simulation values are used as inputs to said circuit design and a time delay is chosen for each electronic component from said set of delay samples associated with each electronic component, wherein the time delay chosen for a first component is independent of the time delay chosen for a second component.
Claim 3
Independent Claim 233 words
A system for simulating and detecting timing errors in a circuit design that includes electronic components, the system comprising: a net list register for storing a net list of electronic components in a circuit design; a model memory register for storing parametric timing constraint data comprising a nominal time delay value for each electronic component in said circuit design; an input value register for storing simulation input values for said circuit design; a sequencer for storing a simulation time period value and for providing notification when the end of said simulation time period is reached; a randomizer for generating and storing a set of delay samples associated with each electronic component as a function of said nominal time delay associated with each electronic component, wherein a greater number of delay samples are generated and stored at said nominal time delay value than at other delay times for each electronic component; and a logic simulator connected to said net list register, model memory register, input value register, sequencer, and randomizer, for simulating the circuit design in order to detect timing errors, wherein said simulation values are used as inputs to said circuit design and a time delay is chosen for each electronic component from said set of delay samples associated with each electronic component, wherein the time delay chosen for a first component is independent of the time delay chosen for a second component.
Claim 4
Independent Claim 233 words
A system for simulating and detecting timing errors in a circuit design that includes electronic components, the system comprising: a net list register for storing a net list of electronic components in a circuit design; a model memory register for storing parametric timing constraint data comprising a nominal time delay value for each electronic component in said circuit design; an input value register for storing simulation input values for said circuit design; a sequencer for storing a simulation time period value and for providing notification when the end of said simulation time period is reached; a randomizer for generating and storing a set of delay samples associated with each electronic component as a function of said nominal time delay associated with each electronic component, wherein a greater number of delay samples are generated and stored at said nominal time delay value than at other delay times for each electronic component; and a logic simulator connected to said net list register, model memory register, input value register, sequencer, and randomizer, for simulating the circuit design in order to detect timing errors, wherein said simulation values are used as inputs to said circuit design and a time delay is chosen for each electronic component from said set of delay samples associated with each electronic component, wherein the time delay chosen for a first component is independent of the time delay chosen for a second component.
Claim 5
Dependent Claim 181 words
In a simulation system, a method for simulating and detecting timing errors in a circuit that includes a plurality of circuit components, each component having a minimum delay and a maximum delay, the method comprising the steps of: randomly generating a set of delay times associated with each component in said circuit design as a function of a range defined by said minimum and said maximum delays for each component, wherein a greater number of delay times are generated at said minimum and said maximum delays than at other delay times for each component; selecting input states to said circuit design; selecting a delay time for each component in said circuit design from said set of delay times associated with each component, wherein the delay time chosen for a first component is independent of the delay time chosen for a second component; and simulating for a fixed time period to detect timing errors in said circuit design with said selected input states applied as inputs to said circuit design and with each said selected delay time applied to each associated component.
Claim 6
Dependent Claim 181 words
In a simulation system, a method for simulating and detecting timing errors in a circuit that includes a plurality of circuit components, each component having a minimum delay and a maximum delay, the method comprising the steps of: randomly generating a set of delay times associated with each component in said circuit design as a function of a range defined by said minimum and said maximum delays for each component, wherein a greater number of delay times are generated at said minimum and said maximum delays than at other delay times for each component; selecting input states to said circuit design; selecting a delay time for each component in said circuit design from said set of delay times associated with each component, wherein the delay time chosen for a first component is independent of the delay time chosen for a second component; and simulating for a fixed time period to detect timing errors in said circuit design with said selected input states applied as inputs to said circuit design and with each said selected delay time applied to each associated component.
Claim 7
Dependent Claim 156 words
In a simulation system, a method for simulating and detecting timing errors in a circuit that includes circuit components each component having a nominal delay time, the method comprising the steps of: randomly generating a set of delay times associated with each component in said circuit design wherein a greater number of delay times are generated at the nominal delay time than at other delay times for each component; selecting input states to said circuit design; selecting a delay time for each component in said circuit design from said set of delay times associated with each component, wherein the delay time chosen for a first component is independent of the delay time chosen for a second component; and simulating for a fixed time period to detect timing errors in said circuit design with said selected input states applied as inputs to said circuit design and with each said selected delay time applied to each associated component.
Claim 8
Dependent Claim 156 words
In a simulation system, a method for simulating and detecting timing errors in a circuit that includes circuit components each component having a nominal delay time, the method comprising the steps of: randomly generating a set of delay times associated with each component in said circuit design wherein a greater number of delay times are generated at the nominal delay time than at other delay times for each component; selecting input states to said circuit design; selecting a delay time for each component in said circuit design from said set of delay times associated with each component, wherein the delay time chosen for a first component is independent of the delay time chosen for a second component; and simulating for a fixed time period to detect timing errors in said circuit design with said selected input states applied as inputs to said circuit design and with each said selected delay time applied to each associated component.

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1998-05-22 1998-11-21 1999-05-23 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 2002-05-22 2002-11-21 2003-05-23 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2006-05-22 2006-11-21 2007-05-23 $7700.00 Window Closed / Lapsed

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