US5293327A
Expired / Lapsed
US
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Method of logic circuit simulation
Assignee: Mitsubishi Electric Corp
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Filing: 1991-06-21
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Granted: 1994-03-08
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Expires: 2011-06-21
Abstract
Abstract A method of logic simulation includes the steps of reading delay time of a logic element itself calculated in advance, converting output logic value of the logic element to a voltage value, forming a circuit equation based on connection information of an output impedance circuit of the logic element, calculating a voltage value at an arbitrary node of the output impedance circuit by solving the circuit equation, and converting a voltage value of an input node of a logic element of the succeeding stage to a logic value.
Inventors
- 👤 Mikio Ikeda
- 👤 Norihiko Kotani
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 08:31
CPC Classifications
G; G06; G06F; G06F30/00; G06F30/30; G06F30/32; G06F30/33
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
123 words
A method of simulating delay time in a logic circuit, comprising the steps of: reading delay time of the logic element itself calculated in advance; converting an output logic value of said logic element to a voltage value; forming a circuit equation based on connection information of an output impedance circuit of said logic element; calculating a voltage value at an arbitrary node of said output impedance circuit by solving said circuit equation; and converting a voltage value of an input node of a logic element in the succeeding stage to a logic value; whereby delay time between an input node of an arbitrary logic element and an input node of an arbitrary logic element of the succeeding stage can be accurately simulated.
Claim 2
Independent Claim
123 words
A method of simulating delay time in a logic circuit, comprising the steps of: reading delay time of the logic element itself calculated in advance; converting an output logic value of said logic element to a voltage value; forming a circuit equation based on connection information of an output impedance circuit of said logic element; calculating a voltage value at an arbitrary node of said output impedance circuit by solving said circuit equation; and converting a voltage value of an input node of a logic element in the succeeding stage to a logic value; whereby delay time between an input node of an arbitrary logic element and an input node of an arbitrary logic element of the succeeding stage can be accurately simulated.
Claim 3
Dependent Claim
16 words
A method according to claim 1, wherein said circuit equation is formed by using Kirchhoff's law.
Claim 4
Dependent Claim
18 words
A method according to claim 1, wherein said circuit equation is formed in advance before starting logic simulation.
Claim 5
Dependent Claim
20 words
A method according to claim 1, wherein delay time of said logic element itself is calculated based on an experiment.
Claim 6
Dependent Claim
19 words
A method according to claim 1, wherein delay time of said logic element itself is calculated by circuit simulation.
References Cited (Backward Citations)
US4590581A
Cited
US4590581B1
Cited
US4775950A
Cited
US4891773A
Cited
US5051941A
Cited
US4922445A
Cited
US4866663A
Cited
US5051911A
Cited
US5084824A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-03-07 | 1997-09-06 | 1998-03-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-03-07 | 2001-09-06 | 2002-03-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-03-07 | 2005-09-06 | 2006-03-08 | $7700.00 | Window Closed / Lapsed |