Patent US5418476A successfully refreshed from Google Patents.
US5418476A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Low voltage output buffer with improved speed
Assignee: Avago Technologies International Sales Pte Ltd
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Filing: 1994-07-28
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Granted: 1995-05-23
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Expires: 2014-07-28
Abstract
Abstract An integrated circuit output buffer that operates at a low power supply voltage (e.g., 3.3 volts) shares an I/O bondpad with input circuitry that operates at a higher voltage (e.g., 5 volt) signal level. The higher voltage signal level is typically obtained by connection of the bondpad to a bus that is connected to one or more output buffers on other IC's that operate at the higher power supply voltage level. The inventive output buffer obtains a decreased propagation delay by the use of an additional pull-up transistor in a configuration that protects the low voltage output transistors, including the additional transistor, from the higher voltage signal levels present on the bondpad. In this manner, the output buffer may be used in applications that require the relatively low propagation delay specified for the PCI bus, for example.
Inventors
- 👤 Mark S. Strauss
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 03:23
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721; H03K19/02; H03K19/08; H03K19/094; H03K19/09425; H03K19/09429
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
133 words
An integrated circuit comprising an output buffer coupled to an output conductor, wherein said output buffer includes a first p-channel pull-up transistor having a gate coupled to receive a buffer input signal, and source and drain regions connected between a positive power supply voltage conductor and said output conductor, and an n-channel pull-down transistor having a gate coupled to receive the buffer input signal, a source coupled to a negative power supply voltage conductor and a drain connected at a given node to a voltage-dropping protective device coupled to said output conductor, characterized in that said integrated circuit further comprises an additional p-channel pull-up transistor having a source coupled to said positive power supply voltage conductor, a drain coupled to said given node, and a gate coupled to receive said buffer input signal.
Claim 2
Dependent Claim
133 words
An integrated circuit comprising an output buffer coupled to an output conductor, wherein said output buffer includes a first p-channel pull-up transistor having a gate coupled to receive a buffer input signal, and source and drain regions connected between a positive power supply voltage conductor and said output conductor, and an n-channel pull-down transistor having a gate coupled to receive the buffer input signal, a source coupled to a negative power supply voltage conductor and a drain connected at a given node to a voltage-dropping protective device coupled to said output conductor, characterized in that said integrated circuit further comprises an additional p-channel pull-up transistor having a source coupled to said positive power supply voltage conductor, a drain coupled to said given node, and a gate coupled to receive said buffer input signal.
Claim 3
Dependent Claim
16 words
The integrated circuit of claim 1 wherein said voltage-dropping protective device is an n-channel voltage-dropping transistor.
Claim 4
Dependent Claim
24 words
The integrated circuit of claim 2 wherein the gate of said n-channel voltage dropping transistor is connected to said positive power supply voltage conductor.
Claim 5
Dependent Claim
51 words
The integrated circuit of claim 1 wherein said buffer input signal is supplied to said p-channel pull-up transistor and said additional p-channel pull-up transistor from the output of a NAND gate circuit that receives a buffer input signal on a first input and a tri-state control signal on a second input.
Claim 6
Independent Claim
176 words
A system including a first integrated circuit having an output buffer operating at a low power supply voltage and connected to a signal bus, and also including a second integrated circuit having an output buffer operating at a higher power supply voltage and also connected to said signal bus; wherein said output buffer of said first integrated circuit includes a first p-channel pull-up transistor having a gate coupled to receive a buffer input signal, and source and drain regions connected between a positive power supply voltage conductor and an output conductor, and an n-channel pull-down transistor having a gate coupled to receive the buffer input signal, a source coupled to a negative power supply voltage conductor and a drain connected at a given node to a voltage-dropping protective device coupled to said output conductor, characterized in that said first integrated circuit further comprises an additional p-channel pull-up transistor having a source coupled to said positive power supply voltage conductor, a drain coupled to said given node, and a gate coupled to receive said buffer input signal.
Claim 7
Independent Claim
176 words
A system including a first integrated circuit having an output buffer operating at a low power supply voltage and connected to a signal bus, and also including a second integrated circuit having an output buffer operating at a higher power supply voltage and also connected to said signal bus; wherein said output buffer of said first integrated circuit includes a first p-channel pull-up transistor having a gate coupled to receive a buffer input signal, and source and drain regions connected between a positive power supply voltage conductor and an output conductor, and an n-channel pull-down transistor having a gate coupled to receive the buffer input signal, a source coupled to a negative power supply voltage conductor and a drain connected at a given node to a voltage-dropping protective device coupled to said output conductor, characterized in that said first integrated circuit further comprises an additional p-channel pull-up transistor having a source coupled to said positive power supply voltage conductor, a drain coupled to said given node, and a gate coupled to receive said buffer input signal.
Claim 8
Dependent Claim
15 words
The system of claim 5 wherein said voltage-dropping protective device is an n-channel voltage-dropping transistor.
Claim 9
Dependent Claim
23 words
The system of claim 6 wherein the gate of said n-channel voltage dropping transistor is connected to said positive power supply voltage conductor.
Claim 10
Dependent Claim
50 words
The system of claim 5 wherein said buffer input signal is supplied to said p-channel pull-up transistor and said additional p-channel pull-up transistor from the output of a NAND gate circuit that receives a buffer input signal on a first input and a tri-state control signal on a second input.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-05-22 | 1998-11-21 | 1999-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-05-22 | 2002-11-21 | 2003-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-05-22 | 2006-11-21 | 2007-05-23 | $7700.00 | Window Closed / Lapsed |