US5239211A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Output buffer circuit
Assignee: NEC Electronics Corp
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Filing: 1991-06-03
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Granted: 1993-08-24
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Expires: 2011-06-03
Abstract
Abstract An output buffer circuit includes a first MOSFET provided between a power supply and an output data terminal and a second MOSFET provided between the output data terminal and the ground. The first and second MOSFETs become ON or OFF state in accordance with outputs of first and second inverter circuits which are controlled by an output potential detecting circuit which detects an output level of the output buffer circuit to avoid the decrease of the ground potential level.
Inventors
- 👤 Toshikatsu Jinbo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 07:11
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/003; H03K19/00346; H03K19/00361
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
140 words
An output buffer circuit, comprising: a first MOSFET provided between a first power supply and an output data terminal; a second MOSFET provided between a second power supply and said output data terminal; a first inverter circuit for supplying a gate of said first MOSFET with a first potential; a second inverter circuit for supplying a gate of said second MOSFET with a second potential; means for detecting a potential of said output data terminal to generate a detecting signal; and means for controlling said first and second inverter circuits in accordance with said detecting signal supplied from said detecting means to avoid sudden change of state in said first or second inverter circuit, including means for delaying a timing of changing said first or second MOSFET from ON state to OFF state, wherein said delaying means is a resistor.
Claim 2
Dependent Claim
140 words
An output buffer circuit, comprising: a first MOSFET provided between a first power supply and an output data terminal; a second MOSFET provided between a second power supply and said output data terminal; a first inverter circuit for supplying a gate of said first MOSFET with a first potential; a second inverter circuit for supplying a gate of said second MOSFET with a second potential; means for detecting a potential of said output data terminal to generate a detecting signal; and means for controlling said first and second inverter circuits in accordance with said detecting signal supplied from said detecting means to avoid sudden change of state in said first or second inverter circuit, including means for delaying a timing of changing said first or second MOSFET from ON state to OFF state, wherein said delaying means is a resistor.
Claim 3
Dependent Claim
142 words
An output buffer circuit, comprising: a first MOSFET provided between a first power supply and an output data terminal; a second MOSFET provided between a second power supply and said output data terminal; a first inverter circuit for supplying a gate of said first MOSFET with a first potential; a second inverter circuit for supplying a gate of said second MOSFET with a second potential; means for detecting a potential of said output data terminal to generate a detecting signal; and means for controlling said first and second inverter circuits in accordance with said detecting signal supplied from said detecting means to avoid sudden change of state in said first or second inverter circuit, including means for delaying a timing of changing said first or second MOSFET from ON state to OFF state, wherein said delaying means is a depletion type MOSFET.
Claim 4
Dependent Claim
142 words
An output buffer circuit, comprising: a first MOSFET provided between a first power supply and an output data terminal; a second MOSFET provided between a second power supply and said output data terminal; a first inverter circuit for supplying a gate of said first MOSFET with a first potential; a second inverter circuit for supplying a gate of said second MOSFET with a second potential; means for detecting a potential of said output data terminal to generate a detecting signal; and means for controlling said first and second inverter circuits in accordance with said detecting signal supplied from said detecting means to avoid sudden change of state in said first or second inverter circuit, including means for delaying a timing of changing said first or second MOSFET from ON state to OFF state, wherein said delaying means is a depletion type MOSFET.
Claim 5
Dependent Claim
162 words
An output buffer circuit comprising: a first MOSFET provided between a first power supply and an output data terminal; a second MOSFET provided between a second power supply and said output data terminal; a first inverter circuit for supplying a gate of said first MOSFET with a first potential; a second inverter circuit for supplying a gate of said second MOSFET with a second potential; means for detecting a potential of said output data terminal to generate a detecting signal; and means for controlling said first and second inverter circuits in accordance with said detecting signal supplied form said detecting means to avoid sudden change of state in said first or second inverter circuit wherein the first inverter includes a third and fourth MOSFET, and the second inverter includes a fifth and sixth MOSFET, and wherein the means for controlling includes a first resistor coupled between the third and fourth MOSFET and a second resistor coupled between the fifth and sixth MOSFET.
Claim 6
Dependent Claim
162 words
An output buffer circuit comprising: a first MOSFET provided between a first power supply and an output data terminal; a second MOSFET provided between a second power supply and said output data terminal; a first inverter circuit for supplying a gate of said first MOSFET with a first potential; a second inverter circuit for supplying a gate of said second MOSFET with a second potential; means for detecting a potential of said output data terminal to generate a detecting signal; and means for controlling said first and second inverter circuits in accordance with said detecting signal supplied form said detecting means to avoid sudden change of state in said first or second inverter circuit wherein the first inverter includes a third and fourth MOSFET, and the second inverter includes a fifth and sixth MOSFET, and wherein the means for controlling includes a first resistor coupled between the third and fourth MOSFET and a second resistor coupled between the fifth and sixth MOSFET.
Claim 7
Dependent Claim
166 words
An output buffer circuit comprising: a first MOSFET provided between a first power supply and an output data terminal; a second MOSFET provided between a second power supply and said output data terminal; a first inverter circuit for supplying a gate of said first MOSFET with a first potential; a second inverter circuit for supplying a gate of said second MOSFET with a second potential; means for detecting a potential of said output data terminal to generate a detecting signal; and means for controlling said first and second inverter circuits in accordance with said detecting signal supplied form said detecting means to avoid sudden change of state in said first or second inverter circuit wherein the first inverter includes a third and fourth MOSFET, and the second inverter includes a fifth and sixth MOSFET, and wherein the means for controlling includes a first depletion type MOSFET coupled between the third and fourth MOSFET and a second depletion type MOSFET coupled between the fifth and sixth MOSFET.
Claim 8
Dependent Claim
166 words
An output buffer circuit comprising: a first MOSFET provided between a first power supply and an output data terminal; a second MOSFET provided between a second power supply and said output data terminal; a first inverter circuit for supplying a gate of said first MOSFET with a first potential; a second inverter circuit for supplying a gate of said second MOSFET with a second potential; means for detecting a potential of said output data terminal to generate a detecting signal; and means for controlling said first and second inverter circuits in accordance with said detecting signal supplied form said detecting means to avoid sudden change of state in said first or second inverter circuit wherein the first inverter includes a third and fourth MOSFET, and the second inverter includes a fifth and sixth MOSFET, and wherein the means for controlling includes a first depletion type MOSFET coupled between the third and fourth MOSFET and a second depletion type MOSFET coupled between the fifth and sixth MOSFET.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-23 | 1997-02-22 | 1997-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-23 | 2001-02-22 | 2001-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-23 | 2005-02-22 | 2005-08-24 | $7700.00 | Window Closed / Lapsed |