Output device capable of high speed operation and operating method thereof

Claim 2

An output device formed on a semiconductor substrate, comprising: an input terminal for receiving an input signal; a reference voltage terminal for receiving a reference voltage; an output terminal connected to a load; a first transistor means having its drain electrode connected to said output terminal and its gate electrode connected to said input terminal, said first transistor means being switched in response to said input signal such that the potential on said output terminal is brought to said reference voltage level; a second transistor means having its drain electrode and gate electrode connected to the source electrode of said first transistor means and its source electrode connected to said reference voltage terminal, said second transistor means being turned off when the level of the output signal supplied through said first transistor means exceeds a predetermined threshold; and current limitation means connected in parallel with said second transistor means for limiting the amount of current passing through said first transistor means when said second transistor means is turned off.

Claim 3

The output device according to claim 1, wherein each of said first transistor means and said second transistor means comprises a MOS transistor having a current handling capability to drive a load at high speed.

Claim 4

The output device according to claim 1, wherein said predetermined level is a threshold voltage of said second transistor means.

Claim 5

The output device according to claim 1, wherein said current limitation means has a resistance which can match with the characteristic impedance of the load.

Claim 6

The output device according to claim 4, wherein said current limitation means includes a MOS transistor and said resistance is a source-drain resistance when the MOS transistor is saturated.

Claim 7

The output device according to claim 1, wherein each of said first transistor means and said second transistor means includes a MOS transistor and said current limitation means includes a diffused resistor so formed as to be in contact with the gate electrode of the MOS transistor included in said second transistor means.

Claim 8

An output device formed on a semiconductor substrate, comprising: an input terminal for receiving an input signal; a first reference voltage terminal for receiving a first reference voltage; a second reference voltage terminal for receiving a second reference voltage; an output terminal connected to a load; a first MOS transistor having its drain electrode connected to said output terminal and its gate electrode connected to said input terminal, said first MOS transistor being switched in response to said input signal such that the potential on said output terminal is brought to said second reference voltage level; a second MOS transistor having its drain electrode and gate electrode connected to the source electrode of said first MOS transistor and its source electrode connected to said first reference voltage terminal, said second MOS transistor being turned off if the level of the output signal supplied through said first MOS transistor means exceeds a predetermined threshold; and a third MOS transistor connected in parallel with respect to said second MOS transistor and having its gate electrode connected to said second reference voltage terminal, said third MOS transistor being turned on in response to said second reference voltage and generating drain-source resistance to match the characteristic impedance of said load, wherein said first and second MOS transistors have current handling capabilities such that they drive said load at high speed.

Claim 9

An output device formed on a semiconductor substrate, comprising: an input terminal for receiving an input signal; a first reference voltage terminal for receiving a first reference voltage; a second reference voltage terminal for receiving a second reference voltage; an output terminal connected to a load; a first MOS transistor having its drain electrode connected to said output terminal and its gate electrode connected to said input terminal, said first MOS transistor being switched in response to said input signal such that the potential on said output terminal is brought to said second reference voltage level; a second MOS transistor having its drain electrode and gate electrode connected to the source electrode of said first MOS transistor and its source electrode connected to said first reference voltage terminal, said second MOS transistor being turned off if the level of the output signal supplied through said first MOS transistor means exceeds a predetermined threshold; and a third MOS transistor connected in parallel with respect to said second MOS transistor and having its gate electrode connected to said second reference voltage terminal, said third MOS transistor being turned on in response to said second reference voltage and generating drain-source resistance to match the characteristic impedance of said load, wherein said first and second MOS transistors have current handling capabilities such that they drive said load at high speed.

Claim 10

The output device according to claim 7, wherein said first, second and third MOS transistors have the same conductivity type.

Claim 11

The output device according to claim 7, wherein one of said first, second and third MOS transistors has a conductivity type different from that of other MOS transistors.

Claim 12

An output device formed on a semiconductor substrate, comprising: an input terminal for receiving an input signal; a reference voltage terminal for receiving a reference voltage; an output terminal connected to a load; a high level output circuit for supplying a signal of high level to said output terminal; and a low level output circuit for supplying a signal of low level to said output terminal, wherein at least one of said high level output circuit and said low level output circuit comprises: a first transistor means having its drain electrode connected to said output terminal and its gate electrode connected to said input terminal, said first transistor means being switched in response to said input signal such that the potential on said output terminal is brought to said reference voltage level; a second transistor means having its drain electrode and gate electrode connected to the source electrode of said first transistor means and its source electrode connected to said reference voltage terminal, said second transistor means being turned off when the level of the output signal supplied through said first transistor means exceeds a predetermined threshold; and means connected in parallel with said second transistor means for limiting the amount of current passing through said first transistor means when said second transistor means is turned off.

Claim 13

An output device formed on a semiconductor substrate, comprising: an input terminal for receiving an input signal; a reference voltage terminal for receiving a reference voltage; an output terminal connected to a load; a high level output circuit for supplying a signal of high level to said output terminal; and a low level output circuit for supplying a signal of low level to said output terminal, wherein at least one of said high level output circuit and said low level output circuit comprises: a first transistor means having its drain electrode connected to said output terminal and its gate electrode connected to said input terminal, said first transistor means being switched in response to said input signal such that the potential on said output terminal is brought to said reference voltage level; a second transistor means having its drain electrode and gate electrode connected to the source electrode of said first transistor means and its source electrode connected to said reference voltage terminal, said second transistor means being turned off when the level of the output signal supplied through said first transistor means exceeds a predetermined threshold; and means connected in parallel with said second transistor means for limiting the amount of current passing through said first transistor means when said second transistor means is turned off.

Claim 14

An output device formed on a semiconductor substrate, comprising: an input terminal for receiving an input signal; a first reference voltage terminal for receiving a first reference voltage; a second reference voltage terminal for receiving a second reference voltage; an output terminal connected to a load; a high level output circuit for supplying a signal of high level to said output terminal; and a low level output circuit for supplying a signal of low level to said output terminal, wherein at least one of said high level output circuit and said low level output circuit comprises: a first MOS transistor having its drain electrode connected to said output terminal and its gate electrode connected to said input terminal, said first MOS transistor being switched in response to said input signal such that the potential on said output terminal is brought to said second reference voltage level; a second MOS transistor having its drain electrode and gate electrode connected to the source electrode of said first MOS transistor and its source electrode connected to said first reference voltage terminal, said second MOS transistor being turned off if the level of the output signal supplied through said first MOS transistor means exceeds a predetermined threshold; and a third MOS transistor connected in parallel with respect to said second MOS transistor and having its gate electrode connected to said second reference voltage terminal, said third MOS transistor being turned on in response to said second reference voltage and generating drain-source resistance to match the characteristic impedance of said load, wherein said first and second MOS transistors have current handling capabilities such that they drive said load at high speed.

Claim 15

An output device formed on a semiconductor substrate, comprising: an input terminal for receiving an input signal; a first reference voltage terminal for receiving a first reference voltage; a second reference voltage terminal for receiving a second reference voltage; an output terminal connected to a load; a high level output circuit for supplying a signal of high level to said output terminal; and a low level output circuit for supplying a signal of low level to said output terminal, wherein at least one of said high level output circuit and said low level output circuit comprises: a first MOS transistor having its drain electrode connected to said output terminal and its gate electrode connected to said input terminal, said first MOS transistor being switched in response to said input signal such that the potential on said output terminal is brought to said second reference voltage level; a second MOS transistor having its drain electrode and gate electrode connected to the source electrode of said first MOS transistor and its source electrode connected to said first reference voltage terminal, said second MOS transistor being turned off if the level of the output signal supplied through said first MOS transistor means exceeds a predetermined threshold; and a third MOS transistor connected in parallel with respect to said second MOS transistor and having its gate electrode connected to said second reference voltage terminal, said third MOS transistor being turned on in response to said second reference voltage and generating drain-source resistance to match the characteristic impedance of said load, wherein said first and second MOS transistors have current handling capabilities such that they drive said load at high speed.

Claim 16

The output device according to claim 11, wherein the first MOS transistor included in said high level output circuit and the first MOS transistor included in said low level output circuit have different conductivity types, the second MOS transistor included in said high level output circuit and the second MOS transistor included in said low level output circuit have different conductivity types, and the third MOS transistor included in said high level output circuit and the third MOS transistor included in said low level output circuit have different conductivity types.

Claim 17

The output device according to claim 12, wherein the first and second MOS transistors included in said high level output circuit have the same conductivity types and the first and second MOS transistors included in said low level output circuit have the same conductivity types.

Claim 18

An output device formed on a semiconductor substrate, comprising: an input terminal for receiving an input signal; a reference voltage terminal for receiving a reference voltage; an output terminal connected to a load; a high level output circuit for supplying a signal of high level to said output terminal; and a low level output circuit for supplying a signal of low level to said output terminal, wherein at least one of said high level output circuit and said low level output circuit comprises: a first transistor means having its gate connected to said input terminal and its drain connected to said reference voltage terminal, said first transistor means being switched in response to said input signal; a second transistor means having its source and gate connected to said output terminal and its drain connected to the source of said first transistor means, said first transistor means being turned off when the level of the potential on said output terminal exceeds a predetermined threshold; and means connected in parallel with said second transistor means for limiting the amount of current passing through said first transistor means when said second transistor means is turned off.

Claim 19

An output device formed on a semiconductor substrate, comprising: an input terminal for receiving an input signal; a reference voltage terminal for receiving a reference voltage; an output terminal connected to a load; a high level output circuit for supplying a signal of high level to said output terminal; and a low level output circuit for supplying a signal of low level to said output terminal, wherein at least one of said high level output circuit and said low level output circuit comprises: a first transistor means having its gate connected to said input terminal and its drain connected to said reference voltage terminal, said first transistor means being switched in response to said input signal; a second transistor means having its source and gate connected to said output terminal and its drain connected to the source of said first transistor means, said first transistor means being turned off when the level of the potential on said output terminal exceeds a predetermined threshold; and means connected in parallel with said second transistor means for limiting the amount of current passing through said first transistor means when said second transistor means is turned off.