Dynamic circuit arrangements

Claim 2

A four-phase electrical dynamic storage element comprising: two controllable components controllable into a conducting or cut-off state in phase opposition; a pair of storage capacitances, each of said storage capacitances lying in parallel with the control path of a different one of said two controllable components and controlling the state of its associated controllable component, a separate charging and a separate discharging circuit for each said capacitance, the discharging circuit of each capacitance consisting of the series connection of the current path of the controllable component associated with the other said pair of capacitances and the current path of a further controllable component which forms a gate, and the charging circuit of each capacitance consisting of a barrierlayer diode whose current path is connected in series with the discharging circuit of the associated capacitance; and generator meAns for supplying cyclically repeated four-phase clock pulses separately to the control inputs of said further controllable components and to one electrode of each of said barrier-layer diodes for causing charging of both said storage capacitances and thereafter discharging of one of said storage capacitances depending on its previous state of charge, the other electrode of each of said barrier-layer diodes being coupled to a respective one of said capacitances for supplying respective clock pulses from said generator means to the associated capacitance as the charging voltage.

Claim 3

A circuit arrangement as claimed in claim 1, in which each of said two controllable components is a respective insulated gate field effect transistor and each said capacitance is formed by the input capacitance of one of said field effect transistors which comprises a respective portion of one of said discharging circuits.

Claim 4

A circuit arrangement as claimed in claim 1, in which each of said barrier-layer diodes is a barrier-layer diode with a p-n junction.

Claim 5

A circuit arrangement as claimed in claim 1, in which each of said barrier-layer diodes is a Schottky diode.

Claim 6

A circuit arrangement as claimed in claim 1 in which said further controllable components are field effect transistors which are changed over from a cut-off to a conducting state, at least partially, by two phases of the repeated clock pulses supplied to their control inputs.

Claim 7

A circuit arrangement as claimed in claim 5, in which the clock pulses are so selected that the charging and discharging circuits of each said capacitance are effective at different times.

Claim 8

A circuit arrangement as claimed in claim 5, in which the clock pulses are staggered in time so that one capacitance first becomes effective for its charging circuit and then for its discharging circuit and that only after the discharging circuit of said one capacitance has has been opened again do the charging and discharging circuits of the other capacitance become effective in succession.

Claim 9

A circuit arrangement as claimed in claim 1, in which each of said two controllable components is a respective insulated gate field effect transistor and each of said capacitances is formed by the input capacitance of one of said transistors, said transistors being connected to one another so that the discharging circuit of the input capacitance of one transistor leads through the controllable current path of the other transistor whose input capacitance forms one of said capacitances.

Claim 10

A circuit arrangement as claimed in claim 8, in which the junction between said charging circuit and discharging circuit of each of said capacitances is connected to the control electrode of said one transistor of the other capacitance, said junctions serving as signal outputs at which the potentials appearing at the capacitances are taken off as an output signal.

Claim 11

A circuit arrangement as claimed in claim 8, in which each of said further controllable components is a respective further insulated gate field effect transistor and wherein the free electrode of each diode is connected to an electrode of the associated one of said transistors forming the capacitances and which is connected in series with the respective diode and one of said further transistors, this connection and the control electrode of each said further transistor of the discharge circuit for each capacitance being connected to said generator means.

Claim 12

A circuit arrangement as claimed in claim 1, in which said arrangement takes the form of an integrated solid-state circuit.

Claim 13

A circuit arrangement as claimed in claim 11, in which all of said diodes and said components are accommodated in a single semiconductor body.

Claim 14

A circuit arrangement as defined in claim 12 wherein each of said charging and discharging circuits comprises: a body of semiconductor material of a first conductivity type; first, second and third spaced regions of the opposite conductivity type formed within said body aNd extending to a single major surface thereof; a fourth region of said first conductivity type formed within said first region and extending to said major surface; a layer of insulating material overlying at least the portions of said semiconductor body which extend to said major surface between said first, second and third regions; first and second metal control electrode layers formed on the surface of said insulating layer and overlying said portions of said body which extend to said surface between said first and second regions and between said second and third regions respectively; and separate electrical contacts for said third and fourth regions whereby said first and fourth regions form a diode, said first and second regions form the source and drain of a first insulated gate field effect transistor and said second and third regions form the source and drain of a second insulated gate field effect transistor with said diode and said first and second transistors all being connected in series.

Claim 15

A circuit arrangement as claimed in claim 5 wherein said further controllable components are insulated gate field effect transistors.

Claim 16

A circuit arrangement as claimed in claim 1 wherein each of said two controllable components and each of said further controllable components are insulated gate field effective transistors.

Claim 17

A circuit arrangement as claimed in claim 1 wherein said two controllable components are respectively a first insulated gate field effect transistor and a second insulated gate field effect transistor; said further controllable components are respectively a third insulated gate field effect transistor and a further insulated gate field effect transistor; the gate electrode of said second field effect transistor is connected to one electrode of one of said diodes which has its other electrode connected to said generator means for receiving clock pulses of the first phase; the gate electrode of said first field effect transistor is connected to one electrode of the other of said diodes which has its other electrode connected to said generator means for receiving clock pulses of the third phase; the gate electrodes of said third and said fourth transistors are connected to said generator means for receiving respectively clock pulses of the second phase and the fourth phase; the first and third field effect transistors are connected in series with one another and said one diode; the second and fourth transistors are connected in series with one another and said other diode; one current carrying electrode of said first field effect transistor is connected to said generator means for receiving clock pulses of the first phase, its other current carrying electrode being connected to a current carrying electrode of said third field effect transistor; and one current carrying electrode of said second field effect transistor is connected to said generator means for receiving clock pulses of the third phase, its other current carrying electrode being connected to a current carrying electrode of said fourth field effect transistor.