Level converting circuit with a bypass transistor

Claim 1

A level converting circuit for converting an input signal having a predetermined potential into an output signal having a different potential and supplying the output signal, comprising: first power supply means for supplying a predetermined first potential; second power supply means for supplying a predetermined second potential lower than said first potential; first inverter means for receiving said input signal and outputting it as an inverted input signal; a first P type transistor, whose source electrode is connected to first power supply means, for receiving said inverted input signal at its gate electrode; a second P type transistor, of which the drain electrode and the gate electrode are connected to each other, the source electrode is connected to said first power supply means and the drain electrode is connected to the drain electrode of said first P type transistor, for outputting the voltage of its gate electrode as said output signal; a first N type transistor, whose drain electrode is connected to the drain electrode of said first P type transistor, for receiving said inverted input signal at its gate electrode; a second N type transistor, of which the gate electrode receives a reference potential having a predetermined level, the drain electrode is connected to the source electrode of said first N type transistor, and the source electrode is connected to said second power supply means, for operating as a constant current source; falling edge detecting means for detecting the fall of said inverted input signal and generating a detection signal; and short-circuiting means responsive to said detection signal for short-circuiting the source electrode and the drain electrode of said second N type transistor for a prescribed duration.