US4963771A
Expired / Lapsed
US
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TTL/CMOS level translator
Assignee: Samsung Semiconductor Inc
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Filing: 1989-09-12
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Granted: 1990-10-16
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Expires: 2009-09-12
Abstract
Abstract The present invention implements a static inverter-type TTL/CMOS level translator. The present invention utilizes a pair of transistors to suppress hot electron effects. The transistor pair limits maximum VDS to VCC-VTN at the first and second gain stages. A pair of resistors serve as a virtual VCC modulator to minimize voltage variations, stabilizing the VIL/VIH trip point. The resistors also minimize standby current so that the translator of the present invention can be used in a low standby current environment. The translator of the present invention provides faster speed, wider process margins, better reliability and lower standby current than prior art translators.
Inventors
- 👤 Shuen-Chin Chang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 14:47
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/0175; H03K19/0185; H03K19/018507; H03K19/018521; H03K19/003; H03K19/00315; H03K19/00369; H03K19/00384
Claims Analysis
Total Claims: 16
Claim 1
Independent Claim
193 words
An electrical circuit for translating transistor-transistor logic (TTL) input voltage levels to complementary metal oxide semiconductor (CMOS) voltage levels comprising: an input stage comprising a first complementary pair of drain coupled first and second transistors of first and second conductivity type, respectively, said first transistor source coupled to a first supply voltage, said second transistor gate coupled to said first supply voltage; a third transistor of said second conductivity type, said third transistor gate coupled to said TTL input, source coupled to ground and drain coupled to the source of said second transistor; said TTL input coupled to the gate of said first transistor; an output stage comprising a second complementary pair of drain coupled fourth and fifth transistors of said first and second conductivity type, respectively, said fourth transistor source coupled to a second supply voltage, said fifth transistor gate coupled to said second supply voltage; a sixth transistor of said second conductivity type, said sixth transistor gate coupled to said drain of said first transistor, source coupled to ground, and drain coupled to the source of said fifth transistor; and said CMOS voltage provided at the drain of said fifth transistor.
Claim 2
Dependent Claim
193 words
An electrical circuit for translating transistor-transistor logic (TTL) input voltage levels to complementary metal oxide semiconductor (CMOS) voltage levels comprising: an input stage comprising a first complementary pair of drain coupled first and second transistors of first and second conductivity type, respectively, said first transistor source coupled to a first supply voltage, said second transistor gate coupled to said first supply voltage; a third transistor of said second conductivity type, said third transistor gate coupled to said TTL input, source coupled to ground and drain coupled to the source of said second transistor; said TTL input coupled to the gate of said first transistor; an output stage comprising a second complementary pair of drain coupled fourth and fifth transistors of said first and second conductivity type, respectively, said fourth transistor source coupled to a second supply voltage, said fifth transistor gate coupled to said second supply voltage; a sixth transistor of said second conductivity type, said sixth transistor gate coupled to said drain of said first transistor, source coupled to ground, and drain coupled to the source of said fifth transistor; and said CMOS voltage provided at the drain of said fifth transistor.
Claim 3
Dependent Claim
40 words
The circuit of claim 1 further including a first resistor coupled between said first supply voltage and the source of said first transistor and a second resistor coupled between said second supply voltage and the source of said fourth transistor.
Claim 4
Dependent Claim
13 words
The circuit of claim 1 wherein said first conductivity type comprises P-type conductivity.
Claim 5
Dependent Claim
195 words
An electrical circuit for translating transistor-transistor logic (TTL) input voltage levels to complementary metal oxide semiconductor (CMOS) voltage levels comprising: an input stage comprising a first complementary pair of drain coupled first and second transistors of first and second conductivity type, respectively, said first transistor source coupled to a first supply voltage, said second transistor gate coupled to said first supply voltage; a plurality of third transistors of said second conductivity type, said third transistors gate coupled to said TTL input, source coupled to ground and drain coupled to the source of said second transistor; said TTL input coupled to the gate of said first transistor; an output stage comprising a second complementary pair of drain coupled fourth and fifth transistors of said first and second conductivity type, respectively, said fourth transistor source coupled to a second supply voltage, said fifth transistor gate coupled to said second supply voltage; a sixth transistor of said second conductivity type, said sixth transistor gate coupled to said drain of said first transistor, source coupled to ground, and drain coupled to the source of said fifth transistor; and said CMOS voltage provided at the drain of said fifth transistor.
Claim 6
Dependent Claim
195 words
An electrical circuit for translating transistor-transistor logic (TTL) input voltage levels to complementary metal oxide semiconductor (CMOS) voltage levels comprising: an input stage comprising a first complementary pair of drain coupled first and second transistors of first and second conductivity type, respectively, said first transistor source coupled to a first supply voltage, said second transistor gate coupled to said first supply voltage; a plurality of third transistors of said second conductivity type, said third transistors gate coupled to said TTL input, source coupled to ground and drain coupled to the source of said second transistor; said TTL input coupled to the gate of said first transistor; an output stage comprising a second complementary pair of drain coupled fourth and fifth transistors of said first and second conductivity type, respectively, said fourth transistor source coupled to a second supply voltage, said fifth transistor gate coupled to said second supply voltage; a sixth transistor of said second conductivity type, said sixth transistor gate coupled to said drain of said first transistor, source coupled to ground, and drain coupled to the source of said fifth transistor; and said CMOS voltage provided at the drain of said fifth transistor.
Claim 7
Dependent Claim
40 words
The circuit of claim 4 further including a first resistor coupled between said first supply voltage and the source of said first transistor and a second resistor coupled between said second supply voltage and the source of said fourth transistor.
Claim 8
Dependent Claim
13 words
The circuit of claim 4 wherein said first conductivity type comprises P-type conductivity.
Claim 9
Dependent Claim
201 words
An electrical circuit for translating transistor-transistor logic (TTL) input voltage levels to complementary metal oxide semiconductor (CMOS) voltage levels comprising: an input stage comprising a first complementary pair of drain coupled first and second transistors of first and second conductivity type, repectively, said first transistor source coupled through a first resistor to a first supply voltage, said second transistor gate coupled to said first supply voltage; a third transistor of said second conductivity type, said third transistor gate coupled to said TTL input, source coupled to ground and drain coupled to the source of said second transistor; said TTL input coupled to the gate of said first transistor; an output stage comprising a second complementary pair of drain coupled fourth and fifth transistors of said first and second conductivity type, respectively, said fourth transistor source coupled through a second resistor to a second supply voltage, said fifth transistor gate coupled to said second supply voltage; a sixth transistor of said second conductivity type, said sixth transistor gate coupled to said drain of said first transistor, source coupled to ground, and drain coupled to the source of said fifth transistor; and said CMOS voltage provided at the drain of said fifth transistor.
Claim 10
Dependent Claim
201 words
An electrical circuit for translating transistor-transistor logic (TTL) input voltage levels to complementary metal oxide semiconductor (CMOS) voltage levels comprising: an input stage comprising a first complementary pair of drain coupled first and second transistors of first and second conductivity type, repectively, said first transistor source coupled through a first resistor to a first supply voltage, said second transistor gate coupled to said first supply voltage; a third transistor of said second conductivity type, said third transistor gate coupled to said TTL input, source coupled to ground and drain coupled to the source of said second transistor; said TTL input coupled to the gate of said first transistor; an output stage comprising a second complementary pair of drain coupled fourth and fifth transistors of said first and second conductivity type, respectively, said fourth transistor source coupled through a second resistor to a second supply voltage, said fifth transistor gate coupled to said second supply voltage; a sixth transistor of said second conductivity type, said sixth transistor gate coupled to said drain of said first transistor, source coupled to ground, and drain coupled to the source of said fifth transistor; and said CMOS voltage provided at the drain of said fifth transistor.
Claim 11
Dependent Claim
13 words
The circuit of claim 7 wherein said first conductivity type comprises P-type conductivity.
Claim 12
Dependent Claim
203 words
An electrical circuit for translating transistor-transistor logic (TTL) input voltage levels to complementary metal oxide semiconductor (CMOS) voltage levels comprising: an input stage comprising a first complementary pair of drain coupled first and second transistors of first and second conductivity type, repectively, said first transistor source coupled through a first resistor to a first supply voltage, said second transistor gate coupled to said first supply voltage; a plurality of third transistors of said second conductivity type, said third transistors gate coupled to said TTL input, source coupled to ground and drain coupled to the source of said second transistor; said TTL input coupled to the gate of said first transistor; an output stage comprising a second complementary pair of drain coupled fourth and fifth transistors of said first and second conductivity type, respectively, said fourth transistor source coupled through a second resistor to a second supply voltage, said fifth transistor gate coupled to said second supply voltage; a sixth transistor of said second conductivity type, said sixth transistor gate coupled to said drain of said first transistor, source coupled to ground, and drain coupled to the source of said fifth transistor; and said CMOS voltage provided at the drain of said fifth transistor.
Claim 13
Dependent Claim
203 words
An electrical circuit for translating transistor-transistor logic (TTL) input voltage levels to complementary metal oxide semiconductor (CMOS) voltage levels comprising: an input stage comprising a first complementary pair of drain coupled first and second transistors of first and second conductivity type, repectively, said first transistor source coupled through a first resistor to a first supply voltage, said second transistor gate coupled to said first supply voltage; a plurality of third transistors of said second conductivity type, said third transistors gate coupled to said TTL input, source coupled to ground and drain coupled to the source of said second transistor; said TTL input coupled to the gate of said first transistor; an output stage comprising a second complementary pair of drain coupled fourth and fifth transistors of said first and second conductivity type, respectively, said fourth transistor source coupled through a second resistor to a second supply voltage, said fifth transistor gate coupled to said second supply voltage; a sixth transistor of said second conductivity type, said sixth transistor gate coupled to said drain of said first transistor, source coupled to ground, and drain coupled to the source of said fifth transistor; and said CMOS voltage provided at the drain of said fifth transistor.
Claim 14
Dependent Claim
13 words
The circuit of claim 9 wherein said first conductivity type comprises P-type conductivity.
Claim 15
Dependent Claim
203 words
An electrical circuit for translating transistor-transistor logic (TTL) input voltage levels to complementary metal oxide semiconductor (CMOS) voltage levels comprising: an input stage comprising a first complementary pair of drain coupled first and second transistors of first and second conductivity type, repectively, said first transistor source coupled through a first resistor to a first supply voltage, said second transistor gate coupled to said first supply voltage; a plurality of third transistors of said second conductivity type, said third transistors gate coupled to said TTL input, source coupled to ground and drain coupled to the source of said second transistor; said TTL input coupled to the gate of said first transistor; an output stage comprising a second complementary pair of drain coupled fourth and fifth transistors of said first and second conductivity type, respectively, said fourth transistor source coupled to a second supply voltage, said fifth transistor gate coupled to said second supply voltage; a sixth transistor of said second conductivity type, said sixth transistor gate coupled to said drain of said first transistor, source coupled through a second resistor to ground, and drain coupled to the source of said fifth transistor; and said CMOS voltage provided at the drain of said fifth transistor.
Claim 16
Dependent Claim
203 words
An electrical circuit for translating transistor-transistor logic (TTL) input voltage levels to complementary metal oxide semiconductor (CMOS) voltage levels comprising: an input stage comprising a first complementary pair of drain coupled first and second transistors of first and second conductivity type, repectively, said first transistor source coupled through a first resistor to a first supply voltage, said second transistor gate coupled to said first supply voltage; a plurality of third transistors of said second conductivity type, said third transistors gate coupled to said TTL input, source coupled to ground and drain coupled to the source of said second transistor; said TTL input coupled to the gate of said first transistor; an output stage comprising a second complementary pair of drain coupled fourth and fifth transistors of said first and second conductivity type, respectively, said fourth transistor source coupled to a second supply voltage, said fifth transistor gate coupled to said second supply voltage; a sixth transistor of said second conductivity type, said sixth transistor gate coupled to said drain of said first transistor, source coupled through a second resistor to ground, and drain coupled to the source of said fifth transistor; and said CMOS voltage provided at the drain of said fifth transistor.
References Cited (Backward Citations)
US4209713A
Cited
US4806801A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1993-10-15 | 1994-04-16 | 1994-10-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-10-15 | 1998-04-16 | 1998-10-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-10-15 | 2002-04-16 | 2002-10-16 | $7700.00 | Window Closed / Lapsed |