Data transfer apparatus having means for controlling the difference in speed between data input/output ports and memory access

Claim 2

A data transfer apparatus, comprising: a plurality of channels, each channel connected to a respective input/output device to which channel numbers are respectively assigned; transfer speed control means interconnected between said channels and a memory, further including monitoring means for monitoring a number of waiting memory accesses from said input/output devices to said memory in each of said channels, the each waiting memory access being generated in response to a difference between a memory access speed and a data entering/exiting speed of said input/output devices; and adjusting means, when the monitoring result detects a predetermined difference, for controlling said input/output devices based on the predetermined difference; wherein, said adjusting means includes a plurality of memory access buffers interconnected between said memory and each of said channels, for storing plural transfer data and accessing said memory; said monitoring means includes a plurality of memory access slot flip-flops arranged in correspondence with the channel numbers, for controlling a memory access time slot of said memory in said respective channels storing the transfer data in said memory access buffers, a memory-side buffer pointer for counting access counts between said memory and each of said memory access buffers in accordance with said channel numbers, and a channel-side buffer pointer for counting access counts between each of said channels and each of said memory access buffers in accordance with said channel numbers; and said adjusting means further includes an arithmetic circuit for calculating a difference between the content of said memory-side buffer pointer and that of said channel-side buffer pointer to output a difference signal in each of said channels, and a changing means for changing a memory access timing when the difference signal exceeds a predetermined value, said changing means multiplexing the memory access time slots corresponding to one of said channels of which the difference signal represents the predetermined value.

Claim 3

A data transfer apparatus, comprising: a plurality of channels each connected to a respective input/output device to which channel numbers are respectively assigned; transfer speed control means interconnected between said channels and a memory, further including a monitoring means for monitoring a number of waiting memory accesses from said input/output devices to said memory in each of said channels, each waiting memory access being generated in response to a difference between a memory access speed and a data entering/exiting speed of said input/output devices; and adjusting means, when the monitoring result detects a predetermined difference, for controlling said input/output devices based on the predetermined difference; wherein, said monitoring means include a plurality of memory access buffers interconnected between said memory and each of said channels for storing plural transfer data and accessing said memory, and measuring means for measuring the transfer speed of each of said input/output devices; said adjusting means including a changing means for changing a correspondence between memory request flags and the channel numbers when the measurement result of said measuring means exceeds a predetermined value, said memory responsive to said memory request flags of a corresponding channel for accessing said transfer data in a corresponding memory access buffer in a time division multiplex fashion said changing means achieving high-speed memory access by assigning at least two of said memory request flags to a given channel when said measuring means measures a transfer speed for greater than a predetermined value in said given channel.

Claim 4

A data transfer apparatus, comprising: a plurality of channels each connected to a respective input/output device to which channel numbers are respectively assigned; transfer speed control means interconnected between said channels and a memory, further including a monitoring means for monitoring a number of waiting memory accesses from said input/output devices to said memory in each of said channels, each waiting memory access being generated in response to a difference between a memory access speed and a data entering/exiting speed of said input/output devices; and adjusting means, when the monitoring result detects a predetermined difference, for controlling said input/output devices based on the predetermined difference; wherein, said monitoring means include a plurality of memory access buffers interconnected between said memory and each of said channels for storing plural transfer data and accessing said memory, and measuring means for measuring the transfer speed of each of said input/output devices; said adjusting means including a changing means for changing a correspondence between memory request flags and the channel numbers when the measurement result of said measuring means exceeds a predetermined value, said memory responsive to said memory request flags of a corresponding channel for accessing said transfer data in a corresponding memory access buffer in a time division multiplex fashion said changing means achieving high-speed memory access by assigning at least two of said memory request flags to a given channel when said measuring means measures a transfer speed for greater than a predetermined value in said given channel.

Claim 5

A data transfer apparatus, comprising: a plurality of channels, each said channel connected to a respective input/output device to which channel numbers are respectively assigned; transfer speed control means interconnected between said channels and a memory, further including monitoring means for monitoring a number of waiting memory accesses from said input/output devices to said memory in each of said channels, the waiting memory accesses being generated in response to a difference between a memory access speed and a data entering/exiting speed of said input/output devices; and adjusting means, when the monitoring result detects a predetermined difference, for controlling said input/output devices based on the predetermined difference; wherein; said adjusting means includes a plurality of memory access buffers, which buffers are interconnected between said memory and each of said channels, for storing plural transfer data to access said memory; said monitoring means, including a plurality of memory request flags assigned in correspondence with the channel numbers, for requesting memory access to said memory in each of said channels by storing the transfer data in said memory access buffers, a memory-side buffer pointer for counting access counts between said memory and each of said memory access buffers in accordance with said channel numbers, and a channel-side buffer pointer for counting access counts between each of said channels and each of said memory access buffers in accordance with said channel numbers; said adjusting means further including an arithmetic circuit for calculating a difference between the content of said memory-side buffer pointer and that of said channel-side buffer pointer in each of said channels, to output a difference signal; and changing means for changing a corresponding relationship between said memory request flags and the channel numbers when the difference signal exceeds a predetermined value, said changing means assigning at least one of memory request flags assigned to non-used channel numbers to a used channel number with the predetermined value.

Claim 6

A data transfer apparatus, comprising: a plurality of channels, each said channel connected to a respective input/output device to which channel numbers are respectively assigned; transfer speed control means interconnected between said channels and a memory, further including monitoring means for monitoring a number of waiting memory accesses from said input/output devices to said memory in each of said channels, the waiting memory accesses being generated in response to a difference between a memory access speed and a data entering/exiting speed of said input/output devices; and adjusting means, when the monitoring result detects a predetermined difference, for controlling said input/output devices based on the predetermined difference; wherein; said adjusting means includes a plurality of memory access buffers, which buffers are interconnected between said memory and each of said channels, for storing plural transfer data to access said memory; said monitoring means, including a plurality of memory request flags assigned in correspondence with the channel numbers, for requesting memory access to said memory in each of said channels by storing the transfer data in said memory access buffers, a memory-side buffer pointer for counting access counts between said memory and each of said memory access buffers in accordance with said channel numbers, and a channel-side buffer pointer for counting access counts between each of said channels and each of said memory access buffers in accordance with said channel numbers; said adjusting means further including an arithmetic circuit for calculating a difference between the content of said memory-side buffer pointer and that of said channel-side buffer pointer in each of said channels, to output a difference signal; and changing means for changing a corresponding relationship between said memory request flags and the channel numbers when the difference signal exceeds a predetermined value, said changing means assigning at least one of memory request flags assigned to non-used channel numbers to a used channel number with the predetermined value.