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US4591973A Expired / Lapsed US ⏱️ 0.0 years remaining

Input/output system and method for digital computers

Assignee: Hughes Training Inc
•
Filing: 1983-06-06
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Granted: 1986-05-27
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Expires: 2003-06-06
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Abstract

Abstract An input/output (I/O) system and method for coupling a host computer to a plurality of peripheral devices in which data destined for peripheral devices is transferred to an output data buffer whose locations are paired with output channel addresses stored in an output device table. A microcomputer performs any processing required on data stored in the output data buffer by reading the address and a function code in the output device table then distributes processed data to an output device block whose locations are addresses of output channels. An input data buffer and input device table similarly arranged, collects and processes input data continuously, which input data buffer can be transferred to the host computer, on command, in a high speed burst.

Inventors

  • 👤 Fred O. Ferris, III
  • 👤 Harri G. Prival

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 06:27
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/20; G06F13/32

Claims Analysis

Total Claims: 5
Claim 1
Independent Claim 285 words
An input/output (I/O) system that selectively couples a host computer to a plurality of external peripheral devices, said host computer having a memory with a plurality of locations for storing data to be transferred to said plurality of prhipheral devices, said I/O system comprising: digital computer means coupled to receive processing and test interrupt signals from said host computer for processing and distributing host computer supplied address, data and control signals to said plurality of external peripheral devices, memory means included in said digital computer means coupled to receive said address, data and control signals from said host computer for storage of said host computer supplied address, data and control signals to be transferred to said plurality of external peripheral devices, a device table in said memory means having a plurality of locations each location for storing a field which contains an address of a selected peripheral device and a function code which may be modified by said host computer during operation for specifying a sub-routine for processing said host computer supplied data by said digital computer means, a data buffer in said memory means having a plurality of locations paired with locations in said device table respectively for receiving address, data and control signals transferred in high speed bursts by said host computer, a device data block in said memory means having a plurality of locations corresponding to addresses in said device table, said locations in said data block being coupled to said external peripheral devices for the transfer thereto of host computer supplied data processed by said digital computer means, and a plurality of I/O modules each including an address circuit for coupling to said device data block locations in said memory means.
Claim 2
Dependent Claim 285 words
An input/output (I/O) system that selectively couples a host computer to a plurality of external peripheral devices, said host computer having a memory with a plurality of locations for storing data to be transferred to said plurality of prhipheral devices, said I/O system comprising: digital computer means coupled to receive processing and test interrupt signals from said host computer for processing and distributing host computer supplied address, data and control signals to said plurality of external peripheral devices, memory means included in said digital computer means coupled to receive said address, data and control signals from said host computer for storage of said host computer supplied address, data and control signals to be transferred to said plurality of external peripheral devices, a device table in said memory means having a plurality of locations each location for storing a field which contains an address of a selected peripheral device and a function code which may be modified by said host computer during operation for specifying a sub-routine for processing said host computer supplied data by said digital computer means, a data buffer in said memory means having a plurality of locations paired with locations in said device table respectively for receiving address, data and control signals transferred in high speed bursts by said host computer, a device data block in said memory means having a plurality of locations corresponding to addresses in said device table, said locations in said data block being coupled to said external peripheral devices for the transfer thereto of host computer supplied data processed by said digital computer means, and a plurality of I/O modules each including an address circuit for coupling to said device data block locations in said memory means.
Claim 3
Dependent Claim 48 words
An input/output (I/O) system as recited in claim 1 further including an I/O system interface means for coupling said host computer to said digital computer means, said I/O interface means configurable to interface selected host computers using high speed data burst transfer techniques to said digital computer means.
Claim 4
Independent Claim 258 words
A method for transferring data from a memory of a host computer to selected external peripheral devices comprising the steps of: pairing locations in a data buffer of an input/output (I/O) system with locations in a device table of said input/output (I/O) system, transferring in high speed bursts address, data and control signals from said memory of said host computer to said data buffer transmitting an output processing interrupt signal from said host computer to a digital computer means in said input/output (I/O) system causing said digital computer means to perform the following steps: reading a first word in said device table causing said digital computer means to transfer and process data stored in a first paired location in said data buffer, said device table words capable of being modified by said host computer during system operation, transferring processed data to an address in a device block in said input/output (I/O) system, said address specified by said first word in said device table transferring said processed data from an address in said device block to a selected peripheral device continuing to read in turn each word in said device table causing said digital computer means to transfer and process data stored in each paired location of said data buffer, transferring said processed data to specified device block addresses for transfer to selected external perhipheral devices, after reading all words in said device table said digital computer means resumes processing input signals from said external peripheral devices until receipt of next output processing interrupt signal from said host computer.
Claim 5
Independent Claim 258 words
A method for transferring data from a memory of a host computer to selected external peripheral devices comprising the steps of: pairing locations in a data buffer of an input/output (I/O) system with locations in a device table of said input/output (I/O) system, transferring in high speed bursts address, data and control signals from said memory of said host computer to said data buffer transmitting an output processing interrupt signal from said host computer to a digital computer means in said input/output (I/O) system causing said digital computer means to perform the following steps: reading a first word in said device table causing said digital computer means to transfer and process data stored in a first paired location in said data buffer, said device table words capable of being modified by said host computer during system operation, transferring processed data to an address in a device block in said input/output (I/O) system, said address specified by said first word in said device table transferring said processed data from an address in said device block to a selected peripheral device continuing to read in turn each word in said device table causing said digital computer means to transfer and process data stored in each paired location of said data buffer, transferring said processed data to specified device block addresses for transfer to selected external perhipheral devices, after reading all words in said device table said digital computer means resumes processing input signals from said external peripheral devices until receipt of next output processing interrupt signal from said host computer.

References Cited (Backward Citations)

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USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1989-05-26 1989-11-25 1990-05-27 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1993-05-26 1993-11-25 1994-05-27 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1997-05-26 1997-11-25 1998-05-27 $7700.00 Window Closed / Lapsed

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