Phase delay compensator using gating signal generated by a synchronizer for loading and shifting of bit pattern to produce clock phases corresponding to frequency changes

Claim 2

Apparatus for maintaining a phase relationship between a clock signal and associated data in a synchronous computer, said apparatus comprising: means for dynamically translating a frequency change in the clock signal to a binary bit pattern defining a phase-shifted clock signal; means fed by said clock signal and a high frequency reference (HFR) clock signal for providing a gating signal in response to said clock signal and HFR clock signal; and means fed by said binary bit pattern for loading and recirculating said binary bit pattern in accordance with respective states of said gating signal to provide phases of said phase-shifted clock signal related to periods of said HFR clock signal.

Claim 3

The apparatus of claim 1 wherein said dynamically translating means includes array means for storing binary information.

Claim 4

The apparatus of claim 2 wherein said dynamically translating means further includes a clock control circuit coupled to said array means.

Claim 5

The apparatus of claim 3 wherein said means for providing said gating signal is a synchronizer.

Claim 6

The apparatus of claim 4 wherein said clock control circuit includes register means for storing binary codes proportional to a change in the frequency of said clock signal or a change in a length of cable connecting sub-assemblies fed by said clock signal.

Claim 7

The apparatus of claim 5 wherein said means for loading and recirculating includes a shift register and said shift register has a shift/load control input fed by said gating signal to control loading and shifting of said shift register.

Claim 8

The apparatus of claim 6 wherein said array means is a PROM.

Claim 9

The apparatus of claim 1 wherein said translating means includes register means for storing binary codes proportional to a change in the frequency of said clock signal or a change in a length of cable connecting sub assemblies fed by said clock signal.

Claim 10

The apparatus of claim 1 wherein said dynamically translating means further includes a clock control circuit coupled to said translating means, and wherein said clock control circuit includes register means for storing binary codes proportional to a change in the frequency of said clock signal or a change in a length of cable connecting sub-assemblies fed by said clock signal.

Claim 13

The method of claim 10 wherein the step of dynamically translating further comprises the step of: loading into a register a binary code proportional to the current length of the cable or the current computer system clock frequency to provide in response thereto said binary bit pattern as an address to a memory.

Claim 14

A phase compensator apparatus for maintaining a phase relationship between a clock signal and associated data signals in a synchronous computer in response to a phase change arising out of a change in the frequency of the computer's system clock, the clock signal associated with said data signal or a change in the length of the cable connecting sub-assemblies of the computer, said apparatus comprising: array means for storing binary bit patterns representing phase-shifted clock signals; register means for storing binary codes proportional to said frequency change, said binary codes providing addressing means to said bit patterns in said array means; clock control circuit means for loading said binary codes into said array means; generating means for producing phases of each of said phase-shifted clock signals; and synchronizer means for providing a gating signal in response to variations in phase between said clock signal and said system clock signal for enabling loading of said binary bit patterns from said array means into said generator means.

Claim 15

A phase compensator apparatus for maintaining a phase relationship between a clock signal and associated data signals in a synchronous computer in response to a phase change arising out of a change in the frequency of the computer's system clock, the clock signal associated with said data signal or a change in the length of the cable connecting sub-assemblies of the computer, said apparatus comprising: array means for storing binary bit patterns representing phase-shifted clock signals; register means for storing binary codes proportional to said frequency change, said binary codes providing addressing means to said bit patterns in said array means; clock control circuit means for loading said binary codes into said array means; generating means for producing phases of each of said phase-shifted clock signals; and synchronizer means for providing a gating signal in response to variations in phase between said clock signal and said system clock signal for enabling loading of said binary bit patterns from said array means into said generator means.

Claim 16

The phase delay compensator apparatus of claim 12 further comprising means for ensuring the integrity of said binary bit pattern loaded into said generator means.