US4386401A
Expired / Lapsed
US
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High speed processing restarting apparatus
Assignee: Unisys Corp
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Filing: 1980-07-28
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Granted: 1983-05-31
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Expires: 2000-07-28
Abstract
Abstract The present apparatus includes logic for stopping timing circuits in a central processing unit and for restarting the timing circuits to produce timing signals synchronized with an asynchronous external signal. The continuous running master clock of the central processing unit is employed to generate a plurality of phase related new clock signals. Logic circuit means are provided to sequentially attempt to employ each of the new clock signals until one of the new clock signals synchronizes with the external asynchronous signal. The logic circuit means include circuits for selecting a new clock signal to be employed by the timing circuits of the central processing unit so that the new clock is synchronized with the external asynchronous signal.
Inventors
- 👤 Steven M. O'Brien
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 16:16
CPC Classifications
G; G06; G06F; G06F1/00; G06F1/04; G06F1/12
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
189 words
In a high speed central processing unit, apparatus for synchronizing new clock signals with an asynchronous external ready signal, comprising: a high speed central processing unit having a continuous running master clock for generating master clock signal, a memory unit having instructions stored therein, means in said central processing unit for requesting an instruction in memory, means in said memory for generating the set ready signal in response to a request for instruction, a phase generator connected to said central processing unit for generating phase signals, means in said central processing unit for generating a signal for stopping said phase generator after a request for an instruction is issued, means connected to said master clock for generating a plurality of the new clock signals which are phase related to said master clock signal, means responsive to said ready signal for sampling said new clock signals to determine which new clock signal will be synchronized with said asynchronous ready signal from said memory, means for selecting one of said new clock signals synchronized with said ready signal, and means for restarting said phase generator with said selected new clock signal.
Claim 2
Dependent Claim
189 words
In a high speed central processing unit, apparatus for synchronizing new clock signals with an asynchronous external ready signal, comprising: a high speed central processing unit having a continuous running master clock for generating master clock signal, a memory unit having instructions stored therein, means in said central processing unit for requesting an instruction in memory, means in said memory for generating the set ready signal in response to a request for instruction, a phase generator connected to said central processing unit for generating phase signals, means in said central processing unit for generating a signal for stopping said phase generator after a request for an instruction is issued, means connected to said master clock for generating a plurality of the new clock signals which are phase related to said master clock signal, means responsive to said ready signal for sampling said new clock signals to determine which new clock signal will be synchronized with said asynchronous ready signal from said memory, means for selecting one of said new clock signals synchronized with said ready signal, and means for restarting said phase generator with said selected new clock signal.
Claim 3
Dependent Claim
37 words
In a high speed central processing unit of the type set forth in claim 1, wherein said means for generating a plurality of new clock signals includes a plurality of outputs associated with each new clock signal.
Claim 4
Dependent Claim
37 words
In a high speed central processing unit of type set forth in said claim 2, wherein said plurality of outputs associated with each new clock signal includes a new clock signal and a delayed new clock signal.
Claim 5
Dependent Claim
61 words
In a high speed central processing unit of the type set forth in claim 3, wherein said means for sampling said new clock signals comprise logic means coupled to said new clock signals and said delayed new clock signals for generating a signal indicating which delayed new clock signal is the first to respond to said ready signal from said memory.
Claim 6
Dependent Claim
67 words
In a high speed central processing unit of the type set forth in claim 4, wherein said means for selecting one of said new clock signals comprises a plurality of bistable devices coupled to the output of the signals indicating which delayed new clock signal is the first to respond to said ready signal for generating a select signal indicating one of said plurality of new clocks.
Claim 7
Dependent Claim
63 words
In a high speed central processing unit of the type set forth in claim 5, wherein said means for selecting one of said new clocks comprises logic gating means coupled to said select signal and to said new clock signals for generating a new clock output, whereby said new clock output is employed to drive said central processing unit and said phase generator.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1986-05-30 | 1986-11-29 | 1987-05-31 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1990-05-30 | 1990-11-29 | 1991-05-31 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1994-05-30 | 1994-11-29 | 1995-05-31 | $7700.00 | Window Closed / Lapsed |