Process for fabricating ULSI CMOS circuits using a single polysilicon gate layer and disposable spacers

Claim 1

A process for fabricating a CMOS integrated circuit on a silicon substrate, said process commencing at a wafer processing stage where N-type and P-type regions have been formed in an upper stratum of the substrate, field isolation regions have been formed on the substrate, and N-channel and P-channel gate structures have been formed, each gate structure having a pair of opposing sidewalls, said process comprising the following steps: (a) depositing a silicon nitride etch-stop layer which blankets the in-process circuitry; (b) depositing a first silicon dioxide layer which blankets the in-process circuitry; (c) performing a first anisotropic spacer etch to form a first set of spacers on the sidewalls of each N-channel gate structure; (d) masking the N-type regions with photoresist; (e) performing a high-dosage N-channel source/drain implant; (f) removing the first set of spacers from the sidewalls of the N-channel gate structures with a wet etch; (g) performing a low-dosage N-channel source/drain implant; (h) removing the first photoresist mask; (i) depositing a second silicon dioxide layer which blankets the in-process circuitry; p1 (j) performing a second anisotropic spacer etch to form a second set of spacers on the sidewalls of each P-channel gate structure; (k) masking the P-type regions with photoresist; (l) performing a high-dosage P-channel source/drain implant; (m) removing the second set of spacers from the sidewalls of the P-channel gate structures; (n) performing a P-channel anti-punchthrough implant; and (o) removing the second photoresist mask.