CMOS process utilizing disposable silicon nitride spacers for making lightly doped drain transistors

Claim 1

A method for fabricating a CMOS device of the LDD type in a semiconductor wafer comprising the steps of forming respective gates overlying p- and n-type regions in said wafer, forming spacers along the respective sides of said gates to form gate-spacer structures overlying said regions, forming a mask comprising a first protective layer and a second overlying resist layer to cover the gate-spacer structures overlying the regions of one conductivity type and portions of the regions of said one conductivity type in which source/drain regions are to be formed and to leave uncovered the gate-spacer structures overlying the regions of the other conductivity type and portions of the regions of said other conductivity type in which source/drain regions are to be formed, implanting exposed surface portions of the regions of the other conductivity type with dopant of said one conductivity type, and, with said first protective layer still in place, modifying the gate-spacer structures that are not covered by said first protective layer.