Data and forward error control coding techniques for digital signals

Claim 2

An encoder, comprising: A) sequence encoding means for encoding each of a plurality of bit sequences of a digital signal into a plurality of first codewords, each first codeword being characterized by a maximum run length below a pre-selected limit, and a cumulative DC-offset below a pre-selected limit, and B) protection encoding means coupled to said sequence encoding means for receiving the first codewords therefrom and generating a plurality of error protection symbols from the first codewords.

Claim 3

The encoder in accordance with claim 1, wherein each of the first codewords is DC balanced.

Claim 4

The encoder in accordance with claim 1, further comprising means coupled to said sequence encoding means and said protection encoding means for forming a block comprising a plurality of the first codewords and a plurality of the error protection symbols.

Claim 5

The encoder in accordance with claim 3 wherein the block-forming means places at least one error protection symbol between first codewords in the block.

Claim 6

The encoder in accordance with claim 4, further comprising means coupled to said protection encoding means for forming binary complements of the error protection symbols.

Claim 7

The encoder in accordance with claim 5, wherein said block forming means is coupled to said complement forming means for receiving the complements therefrom, and forming a plurality of complement pairs, each complement pair including one of the error protection symbols and its complement, and said block forming means placing at least one of the pairs between a first and second one of said plurality of first codewords within the block.

Claim 8

The encoder in accordance with claim 6, wherein each block includes 96 bits.

Claim 9

The encoder in accordance with claim 7, wherein each block includes four 20-bit first codewords, eight bits of error protection symbols, and eight bits of the complement to said error protection symbols.

Claim 10

The encoder in accordance with claim 8, wherein the first codewords each have 3/4/3 maximum run lengths, and said block has a maximum run length of 4.

Claim 11

The encoder in accordance with claim 9, wherein each sequence includes 16 bits, and said sequence encoding means encodes each sequence into one of the 20-bit first codewords.

Claim 12

The encoder in accordance with claim 10, wherein said sequence encoding means encodes each 16-bit sequence into a 10-bit second codeword and a 10-bit third codeword, which together comprise the first codeword for the sequence.

Claim 13

The encoder in accordance with claim 11, wherein said block forming means forms each block from four of the second codewords and four of the third codewords, and places a complement pair between each of the second and third codewords and at one of the ends of the block.

Claim 14

The encoder in accordance with claim 10, wherein said sequence encoding means encodes each 16-bit sequence into a 9-bit second codeword and an 11-bit third codeword, which together comprise the first codeword for the sequence.

Claim 15

The encoder in accordance with claim 13, wherein said block forming means forms each block from four of the second codewords and four of the third codewords, and places a complement pair between each of the second and third codewords and at one of the ends of the block.

Claim 16

An encoder, comprising: A) protection encoding means for receiving a plurality of bit sequences of a digital signal, and generating a plurality of error protection symbols from the bit sequences, and B) means coupled to said protection encoding means for forming the binary complements of the error protection symbols.

Claim 17

An encoder, comprising: A) protection encoding means for receiving a plurality of bit sequences of a digital signal, and generating a plurality of error protection symbols from the bit sequences, and B) means coupled to said protection encoding means for forming the binary complements of the error protection symbols.

Claim 18

The encoder in accordance with claim 15, further comprising means coupled to said protection encoding means and said complement forming means for forming a block comprising a sub-plurality of the bit sequences, the error protection symbols generated from the sub-plurality of bit sequences, and their complements.

Claim 19

The encoder in accordance with claim 16, wherein said block-forming means places at least one error protection symbol between bit sequences in the block.

Claim 20

The encoder in accordance with claim 17, wherein said block forming means forms a plurality of complement pairs, each complement pair including one of the error protection symbols and its complement, and places at least one of the complement pairs between a first and second one of the bit sequences within the block.

Claim 21

The encoder in accordance with claim 18, wherein said block forming means places one of the complement pairs between every two of the bit sequences.

Claim 22

Apparatus for decoding a block of digitally represented information comprising a plurality of data words and a plurality of pairs of error protection symbols, said data words being serially arranged in said block such that each of said data words is disposed adjacent to at least one other of said data words, each of said data words including a plurality of boundaries, each said error protection symbol pair including an error symbol and a binary complement for said error symbol, said boundaries of adjacent data words having therebetween one of said error protection symbol pairs, said decoder comprising: A) a framer responsive to said error protection symbol pairs for determining said boundaries of said data words within said block, thereby identifying said data words and said error protection symbols; and B) protection decoding means coupled to said framer and responsive to said error protection symbols for detecting any errors in said data words.

Claim 23

Apparatus for decoding a block of digitally represented information comprising a plurality of data words and a plurality of pairs of error protection symbols, said data words being serially arranged in said block such that each of said data words is disposed adjacent to at least one other of said data words, each of said data words including a plurality of boundaries, each said error protection symbol pair including an error symbol and a binary complement for said error symbol, said boundaries of adjacent data words having therebetween one of said error protection symbol pairs, said decoder comprising: A) a framer responsive to said error protection symbol pairs for determining said boundaries of said data words within said block, thereby identifying said data words and said error protection symbols; and B) protection decoding means coupled to said framer and responsive to said error protection symbols for detecting any errors in said data words.

Claim 24

The apparatus in accordance with claim 20, wherein each of said data words comprises a codeword into which data has been encoded, and said apparatus further includes sequence decoding means coupled with said framer for decoding said codewords into a plurality of data sequences, each said first codeword being characterized by a maximum run length below a pre-selected limit, and a cumulative DC-offset below a pre-selected limit.

Claim 25

A communication system comprising: A) a transmitter section including: (1) an encoder comprising a. protection encoding means for receiving a plurality of bit sequences of a digital signal, and generating a plurality of error protection symbols from said bit sequences, b. complement-forming means coupled to said protection encoding means for forming a binary complement for each of said error protection symbols, and c. block-forming means coupled to said protection encoding means and said complement-forming means for forming a plurality of first blocks, each of said first blocks having a bit length and comprising a plurality of said bit sequences, said error protection symbols generated from said bit sequences, and said complements corresponding to said error protection symbols, such that each of said data words has a boundary disposed adjacent to a boundary of at least one other of said data words, said boundaries of adjacent data words having therebetween an error protection pair of symbols comprising one of said error protection symbols and the corresponding complement thereto, (2) a transmitter for sending a communication signal including said first blocks over a channel; and B) a receiver section including: (1) a receiver for receiving said communication signal, and thereby receiving said first blocks, (2) framer means responsive to said error protection symbol pairs for determining said boundaries of said data words within said first blocks, thereby identifying said data words and said error protection symbols; and (3) protection decoding means coupled to said framer means for using said error protection symbols to detect any errors in said data words.

Claim 26

A communication system comprising: A) a transmitter section including: (1) an encoder comprising a. protection encoding means for receiving a plurality of bit sequences of a digital signal, and generating a plurality of error protection symbols from said bit sequences, b. complement-forming means coupled to said protection encoding means for forming a binary complement for each of said error protection symbols, and c. block-forming means coupled to said protection encoding means and said complement-forming means for forming a plurality of first blocks, each of said first blocks having a bit length and comprising a plurality of said bit sequences, said error protection symbols generated from said bit sequences, and said complements corresponding to said error protection symbols, such that each of said data words has a boundary disposed adjacent to a boundary of at least one other of said data words, said boundaries of adjacent data words having therebetween an error protection pair of symbols comprising one of said error protection symbols and the corresponding complement thereto, (2) a transmitter for sending a communication signal including said first blocks over a channel; and B) a receiver section including: (1) a receiver for receiving said communication signal, and thereby receiving said first blocks, (2) framer means responsive to said error protection symbol pairs for determining said boundaries of said data words within said first blocks, thereby identifying said data words and said error protection symbols; and (3) protection decoding means coupled to said framer means for using said error protection symbols to detect any errors in said data words.

Claim 27

The communication system in accordance with claim 22, wherein said framer means comprises: A) block-separation means responsive to a slip signal for separating said communication signal into a plurality of second blocks, each said second blocks having the same bit length and corresponding boundaries as each of said first blocks, and having a plurality of bits occupying a plurality of first bit positions corresponding to said bit sequences of said first blocks, a plurality of bits occupying a plurality of second bit positions corresponding to said error protection symbols, and a plurality of bits occupying a plurality of third bit positions corresponding to said complements of said error protection symbols, B) a sequence error detector coupled with said block-separation means and responsive to said bits occupying said second bit positions corresponding to said error protection symbols for generating a first error signal indicative of the number of errors, if any, in said bits occupying said first bit positions corresponding to said bit sequences of said first blocks, C) a complement-pair-error detector coupled with said block-separation means and responsive to said bits occupying said second bit positions corresponding to said error protection pairs of symbols for generating a second error signal indicative of the number of such pairs, if any, that are not binary complements of one another, and thus represent complement errors; and D) error counter means for counting said number of errors indicated by said first and second error signals, and, if said number exceeds a pre-selected threshold, sending said slip signal to said separation means for redefining said boundaries of said second blocks.