Error detecting device for synchronous data transmission system

Claim 2

Error detecting device for synchronous data transmission system in which data bit groups are transmitted between a transmit station and a receive station, including parity bit generating means at said transmit station and parity checking means at said receive station, characterized in that: said parity generating means produce alternate even and odd parity bits for succeeding data bit groups and said parity checking means check the succeeding data bit groups for alternating even and odd parity.

Claim 3

Device according to claim 1, further comprising: a multi-line transmission bus interconnecting said transmit station and said receive station, the number of lines corresponding to the number of data bits in an individual data bit group plus a parity bit, means at said transmit station for transmitting said data bit groups and associated parity bits over said transmission bus, and means at said receive station for checking said transmitted data bit groups and said parity bits.

Claim 4

Device according to claim 1, further comprising: a single transmission line interconnecting said transmit station and said receive station; means at said transmit station for serializing said data bit groups and parity check bits for transmission to said receive station; and means at said receive station for deserializing said received data bit groups and parity check bits.

Claim 5

Device according to claims 1, 2 or 3, wherein said data bit groups are bytes of information, each byte comprising a predetermined number of data bits plus a parity check bit.

Claim 6

Device according to any one of claims 1 to 4, further comprising: means for controlling said system to transmit and receive said data bit groups as frames of information, each frame comprising a predetermined number of data bit groups, longitudinal redundancy c§eck (LRC) generating means at said transmits station for analyzing signals representative of each data bit position of a frame of said transmitted data bit groups but not including the parity bit position and for producing a longitudinal redundancy check (LRC) for each transmitted data bit position, and longitudinal redundancy check (LRC) checking means at the receive station responsive to received signals representative of each parity bit position other than the parity bit position in the data bit groups for producing a signal upon detection of any LRC error.

Claim 7

Device according to any one of the preceding claims, further comprising: a microprocessor controller for controlling and checking status of said transmit station and said receive station and other functions including generation and checking of said even-odd parity, registers for storing command, status, and checking information, a data bus buffer, a direct memory access control logic, a data bus, and means interconnecting said microprocessor controller with said registers, buffer, logic, and data bus for control and monitoring of system operation.

Claim 8

Device according to claim 6, wherein said microprocessor controller further comprises: timing, synchronizing, transmit byte count and control receive byte count and control circuits, and read/write, cycle steal, control tag, and interrupt circuits for use in transmission and reception of data and checking of said data.

Claim 9

Device according to claim 7, further comprising: (a) the following elements incorporated in said transmit station: a data/parity register, an even-odd parity generating circuit, an LRC generating circuit, signal drive circuits, circuit interconnections for the aforementioned elements, data lines connected to said microprocessor for transfer of data to said transmit stations, transmit gating means responsive to control signal from said microprocessor for gating data, even-odd parity and LRC circuits at said transmit station, (b) the following elements incorporated in said receive station: data/parity receive circuits, an input register, an even-odd parity checking circuit, an LRC checking circuit, a fault (error) indicating circuit, data/parity lines connected to said microprocessor for transfer of data from said receive station, and receive gating means responsive to control signals from said microprocessor for gating data, even-odd parity, LRC and fault indicating circuits at said receive station.

Claim 10

Device according to claim 8 wherein said receive gating means gates data and parity from said receive circuits to said input register for utilization.

Claim 11

Device according to claim 8 or 9 wherein said transmit gating means is operable to gate data and parity information to said transmit data/parity register from an external source and wherein said receive gating means is operable to gate data and parity information from said input register to an external utilization device.