Method and apparatus for reducing DC components in a digital information signal

Claim 2

In a method of recording a digital information signal comprised of a plurality of N-bit data words by means of a recording apparatus which imperfectly transmits DC components of said digital information signal, the steps of: selectively generating M-bit data words in which M is an even integer greater than N and each of said N-bit data words and M-bit data words is comprised of a plurality of logic level "1" bits and logic level "0" bits; weighting each of said M-bit data words on the basis of a first value corresponding to a number, in the M-bit data word, of boundaries between adjacent "1" and "0" bits, a second value corresponding to the number of said "1" bits in the M-bit data word, and a third value corresponding to the numbers, in the M-bit data word, of isolated "1" and "0" bits bounded on both sides by "0" and "1" bits, respectively, and of isolated pairs of "1" and "0" bits bounded on both sides by "0" and "1" bits, respectively; grouping the weighted M-bit data words in accordance with the run length of data thereof; assigning each of said N-bit data words to at least a respective one of said M-bit data words in accordance with the generation frequencies of said N-bit data words so that the run lengths of the assigned M-bit data words will vary generally inversely in respect to the generation frequencies of the respective N-bit data words; converting said N-bit data words to said respective assigned M-bit data words; and recording on a record medium said M-bit data words to which said N-bit data words are converted so as to minimize DC components of the recorded digital information signal and to concentrate the frequency spectrum.

Claim 3

The method according to claim 1 in which the step of grouping said M-bit data words by weight includes the step of forming two coding maps of said M-bit data words, each coding map including 2 N M-bit data words, and each of said N-bit data words being selectively assigned to a respective one of said M-bit data words from each of said two coding maps.

Claim 4

The method according to claim 1; in which said number of isolated "1" and "0" bits is weighted by a factor of one and the number of isolated pairs of "1" and "0" bits is weighted by a factor of two, wherein said third value for each M-bit data word is obtained by adding the number of isolated "1" and "0" bits to twice the number of isolated pairs of "1" and "0" bits.

Claim 5

The method according to claim 1; in which said M-bit data words each have an even number of bits and in which the step of grouping said M-bit data words by weight further includes the step of arranging said M-bit data words in a priority order with M-bit data words of the highest priority having the highest third value, the highest first value and a second value of M/2.

Claim 6

The method according to claim 4; in which the step of arranging said M-bit data words in a priority order includes the steps of obtaining M-bit data words having said highest priority; changing the second value by one so that the number of "1" and "0" bits in the arranged M-bit data words differs by two; decreasing the first value by one and repeating the step of changing the second value; repeating the step of decreasing the first value until no more M-bit data words satisfy the remaining combinations of first and second values with said third value; decreasing the third value and obtaining any M-bit data words having said decreased third value, the highest first value and a second value of M/2; and repeating the steps of changing the second value to one through the step of decreasing the third value, until no more M-bit data words satisfy the remaining combinations of first, second and third values.

Claim 7

The method according to claim 5; in which N equals 8 and M equals 10 and the priority order for obtaining 256 M-bit words is determined by respective third, first and second values of 10,9,5; 10,8,5; 10,8,6; 10,7,5; 10,7,6; 10,6,5; 10,6,6; 10,5,5; 10,5,6; 7,7,6; 7,6,5; 7,6,6; 7,5,5; 7,5,6; 7,4,5.

Claim 8

The method according to claim 2; in which the step of assigning selectively assigns each of said N-bit data words to a respective one of said M-bit data words from one of said coding maps in accordance with the number of "1" bits in each M-bit data word.

Claim 9

The method according to claim 7; in which the step of grouping said M-bit data words by weight includes the step of grouping said M-bit data words into a first group consisting of M-bit data words having an equal number of "1" and "0" bits, a second group consisting of M-bit data words having the number of "1" bits greater than the number of "0" bits, and a third group consisting of M-bit data words having the number of "0" bits greater than the number of "1" bits.

Claim 10

The method according to claim 8; in which one of said coding maps includes M-bit data words from said first and second groups and the other of said coding maps includes M-bit data words from said first and third groups.

Claim 11

The method according to claim 8; in which the step of assigning alternately supplies M-bit data words from said two coding maps for M-bit data words having unequal numbers of "1" and "0" bits.

Claim 12

The method according to claim 8; in which the M-bit data words in the third group are obtained by inverting each "1" and "0" bit of the M-bit data words in the second group.

Claim 13

The method according to claim 9; in which each coding map includes an equal number of M-bit data words, the M-bit data words from said first group being identical in both of said maps, and the M-bit data words in the third group being identical to inverted M-bit data words in the second group.

Claim 14

The method according to claim 12; in which M is equal to 10 and N is equal to 8, and each map includes 256 M-bit data words.

Claim 15

In a method of recording a digital information signal comprised of a plurality of N-bit data words by means of a recording apparatus which imperfectly transmits DC components of said digital information signal, the steps of: selectively generating M-bit data words in which M is an even integer larger than N and each of said N-bit and M-bit data words is comprised of a plurality of logic level "1" bits and logic level "0" bits; weighting each of said M-bit data words on the basis of a first value corresponding to a number of boundaries between adjacent "1" and "0" bits in the M-bit data word, a second value corresponding to the number of said "1" bits in the M-bit data word, and a third value corresponding to the numbers, in the M-bit data word, of isolated "1" and "0" bits and of isolated pairs of "1" and "0" bits bounded on both sides by "0" and "1" bits, respectively; grouping the weighted M-bit data words in accordance with the run length of data thereof; classifying the grouped M-bit data words into a first group consisting of said M-bit data words which have an equal number of said "1" and "0" bits, a second group consisting of said M-bit data words which have a number of said "1" bits greater than the number of said "0" bits, and a third group consisting of said M-bit data words which have a number of said "0" bits greater than the number of said "1" bits; assigning each of said N-bit data words to at least a respective one of said M-bit data words in accordance with the generation frequencies of said N-bit data words so that the run lengths of the assigned M-bit data words will vary generally inversely in respect to the generation frequencies of the respective N-bit data words, with some of said N-bit data words being assigned alternately to said M-bit data words of said second and third groups and the remainder of said N-bit data words being assigned to said M-bit data words of said first group; converting said N-bit data words to said respective assigned M-bit data words so as to minimize DC components of the digital information signal, as converted, and to concentrate its frequency spectrum; and recording on a record medium said M-bit data words to which said N-bit data words have been converted.

Claim 16

In a method of recording a digital information signal comprised of a plurality of N-bit data words by means of a recording apparatus which imperfectly transmits DC components of said digital information signal, the steps of: selectively generating M-bit data words in which M is an even integer larger than N and each of said N-bit and M-bit data words is comprised of a plurality of logic level "1" bits and logic level "0" bits; weighting each of said M-bit data words on the basis of a first value corresponding to a number of boundaries between adjacent "1" and "0" bits in the M-bit data word, a second value corresponding to the number of said "1" bits in the M-bit data word, and a third value corresponding to the numbers, in the M-bit data word, of isolated "1" and "0" bits and of isolated pairs of "1" and "0" bits bounded on both sides by "0" and "1" bits, respectively; grouping the weighted M-bit data words in accordance with the run length of data thereof; classifying the grouped M-bit data words into a first group consisting of said M-bit data words which have an equal number of said "1" and "0" bits, a second group consisting of said M-bit data words which have a number of said "1" bits greater than the number of said "0" bits, and a third group consisting of said M-bit data words which have a number of said "0" bits greater than the number of said "1" bits; assigning each of said N-bit data words to at least a respective one of said M-bit data words in accordance with the generation frequencies of said N-bit data words so that the run lengths of the assigned M-bit data words will vary generally inversely in respect to the generation frequencies of the respective N-bit data words, with some of said N-bit data words being assigned alternately to said M-bit data words of said second and third groups and the remainder of said N-bit data words being assigned to said M-bit data words of said first group; converting said N-bit data words to said respective assigned M-bit data words so as to minimize DC components of the digital information signal, as converted, and to concentrate its frequency spectrum; and recording on a record medium said M-bit data words to which said N-bit data words have been converted.

Claim 17

The method according to claim 14; in which said M-bit data words of one of said second and third groups are each inverted with respect to corresponding M-bit data words of the other of said second and third groups.

Claim 18

The method according to claim 14; in which the assignment of one of said M-bit data words from one of said second and third groups results in the next M-bit data word from one of said second and third groups being assigned from the other of said second and third groups.

Claim 19

The method according to claim 14; further comprising the step of mapping said first and second groups into a first coding map and mapping said first and third groups into a second coding map.

Claim 20

Apparatus for reducing DC components in a digital information signal to be recorded and comprised of a plurality of N-bit data words by converting said N-bit data words to respective M-bit data words at least some of which are assigned thereto in accordance with the generation frequency of said N-bit data words and the run length of data of said M-bit data words, comprising: output means for receiving said M-bit data words; memory means for storing said M-bit data words either in the actual or inverted form thereof and which are read therefrom in response to said N-bit data words; each of said M-bit data words being comprised of a plurality of logic level "1" bits and logic level "0" bits and being stored in said memory means with the number of said "1" bits being greater than or equal to the number of said "0" bits; transmitting means connected with said memory means for transmitting said stored M-bit data words read from said memory means to said output means; inverting means connected with said memory means for inverting said stored M-bit data words read from said memory means and supplying said inverted M-bit data words to said output means; and gate means selectively enabling one of said transmitting means and inverting means to supply said transmitted M-bit data words and said inverted M-bit data words, respectively, to said output means, said transmitting means being enabled whenever an M-bit data word read from said memory means has an equal number of said "1" and "0" bits and said transmitting means and inverting means being alternately enabled when M-bit data words successively read from said memory means have unequal numbers of said "1" and "0" bits.

Claim 21

Apparatus for reducing DC components in a digital information signal to be recorded and comprised of a plurality of N-bit data words by converting said N-bit data words to respective M-bit data words at least some of which are assigned thereto in accordance with the generation frequency of said N-bit data words and the run length of data of said M-bit data words, comprising: output means for receiving said M-bit data words; memory means for storing said M-bit data words either in the actual or inverted form thereof and which are read therefrom in response to said N-bit data words; each of said M-bit data words being comprised of a plurality of logic level "1" bits and logic level "0" bits and being stored in said memory means with the number of said "1" bits being greater than or equal to the number of said "0" bits; transmitting means connected with said memory means for transmitting said stored M-bit data words read from said memory means to said output means; inverting means connected with said memory means for inverting said stored M-bit data words read from said memory means and supplying said inverted M-bit data words to said output means; and gate means selectively enabling one of said transmitting means and inverting means to supply said transmitted M-bit data words and said inverted M-bit data words, respectively, to said output means, said transmitting means being enabled whenever an M-bit data word read from said memory means has an equal number of said "1" and "0" bits and said transmitting means and inverting means being alternately enabled when M-bit data words successively read from said memory means have unequal numbers of said "1" and "0" bits.

Claim 22

The apparatus according to claim 18; in which said transmitting means includes a buffer circuit and said inverting means includes an inverter circuit, each having an input for enabling the operation thereof.

Claim 23

The apparatus according to claim 18; in which said memory means has a flag terminal which produces an output signal of a first value when an M-bit data word read therefrom has an equal number of "1" and "0" bits and which is of a second value when an M-bit data word read therefrom has an unequal number of "1" and "0" bits.

Claim 24

The apparatus according to claim 20; in which said gate means includes flip-flop means for producing an output signal in response to said output signal from said flag terminal and means for enabling one of said transmitting means and inverting means in response to said output signals from said flip-flop means and said flag terminal.

Claim 25

The apparatus according to claim 21; in which said flip-flop means is a J-K flip-flop having a J input terminal and a K input terminal; said apparatus further including a first AND gate and a first NAND gate, each supplied with the output signal from said flag terminal and with a data pickup pulse, said AND gate supplying an output signal to said J input terminal and said NAND gate supplying an output signal to said K input terminal; and said means for enabling including a second AND gate supplied with the output signals from said J-K flip-flop and said first AND gate and producing an output signal in response thereto, an inverter circuit for inverting said output signal from said second AND gate, a second NAND gate for enabling said transmitting means in response to said inverted output signal and said data pickup pulse, and a third NAND gate for enabling said inverting means in response to said output signal from said second AND gate and said data pickup pulse.