EP0250049A1
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Channel encoder
Assignee: Koninklijke Philips NV
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Filing: 1987-06-16
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Granted: —
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Expires: 2007-06-16
Abstract
Abstract On the basis of n-bit words presented, the described channel encoder generates DC-free and run length limited m-bit (m n) code words having (1 + D) -1 or (1 + D2) -1 precoder properties. The m-bit code words are formed each time by appending (m-n) bits to the n-bit words presented. For the determination of the (m-n) bits to be added, the amplitude density function as well as the distribution of the run length and the digital sum variation of the code words is calculated.
Inventors
- 👤 Wilhelmus Jacobus Van Gestel
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 07:55
CPC Classifications
H; H03; H03M; H03M7/00; G; G11; G11B; G11B20/00; G11B20/10; G11B20/14; G11B20/1403; G11B20/1423; G11B20/1426; H03M5/00; H03M5/02; H03M5/04; H03M5/14; H03M5/145
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
142 words
A channel encoder for encoding received n-bits information words to m-bits, mainly DC-free code words, where m > n, which channel encoder comprises a memory circuit having an input connected to a counter, which memory circuit is provided for receiving each time the n-bits information word and which counter is provided for determining the digital sum variation (DSV) between two successive received binary words, characterized in that the encoder comprises a precoder which is provided for supplying at an output of said encoder and to an input of said counter m-bits code word which is run length limited (RLL) and which is derived from the n-bits information word supplied to an input of said precoder in series with an (m-n)-bits word formed by said memory circuit on the basis of such digital sum variation and the digital sum of the m-bits codeword.
Claim 2
Dependent Claim
142 words
A channel encoder for encoding received n-bits information words to m-bits, mainly DC-free code words, where m > n, which channel encoder comprises a memory circuit having an input connected to a counter, which memory circuit is provided for receiving each time the n-bits information word and which counter is provided for determining the digital sum variation (DSV) between two successive received binary words, characterized in that the encoder comprises a precoder which is provided for supplying at an output of said encoder and to an input of said counter m-bits code word which is run length limited (RLL) and which is derived from the n-bits information word supplied to an input of said precoder in series with an (m-n)-bits word formed by said memory circuit on the basis of such digital sum variation and the digital sum of the m-bits codeword.
Claim 3
Dependent Claim
68 words
A channel encoder as claimed in Claim 1, characterized in that (m-n) = 1, the precoder having a transfer function (1 + D) -1 , D being the delay operator, said precoder output being connected to a further input of said memory circuit for inputting only the last bit of a preceding m-bit code word, said last bit being considered for forming said (m-n) = 1 bit word.
Claim 4
Dependent Claim
74 words
A channel encoder as claimed in Claim 2, characterized in that the memory circuit comprises a memory wherein there is stored the digital sum for each of the m-bits code words having passed the precoder following an m-bits codeword which last bit has a first predetermined value and which m-bits codewords being formed each time from a respective n-bits information word to which a 1-bit word having a second predetermined value has been appended.
Claim 5
Dependent Claim
105 words
A channel encoder as claimed in Claim 3, characterized in that the memory circuit also includes a logic circuit connected to a data output of said memory and having the transfer function y = x 1 x 2 x 3 + X 1 x 2 x 3 + X 1 X 2 x + x 1 x 2x3 where x1 represents a standard for the relevant digital sum value (DS), x2 represents said last bit supplied by the precoder, and x3 represents a standard for said digital sum variation (DSV), y being the value of the bit to be appended to the n-bit information word.
Claim 6
Dependent Claim
69 words
A channel encoder as claimed in Claim 4, characterized in that said encoder comprises a zero detector whereto the n-bit information word is applied and which supplies a zero detection signal when the n-bit information word consists only of zeroes, said zero detection signal respectively said signal y being applied to a first respectively a second input of a logic OR-gate at which output- said 1-bit word being supplied.
Claim 7
Dependent Claim
67 words
A channel encoder as claimed in Claim 1, characterized in that m-n = 2 and that the precoder has a transfer function (1 + D 2 ) -1 , D being the delay operator, only the last two bits (x m , x m-1 ) of the preceding m-bit code word being used for determining the 2-bit encoding signal to be added to the n-bit information word.
Claim 8
Dependent Claim
85 words
A channel encoder as claimed in Claim 6, characterized in that in the memory circuit is provided for forming a 2-bit word (x a , x b ) upon reception of the n-bit information word and said digital sum variation, the memory circuit further comprises two EXCUSIVE-OR gates which, in response to the bits x a and x b and to the bits x m and x m-1 , supply the bits x' a and xb, respectively, to be added to the n-bit information word.
Claim 9
Dependent Claim
100 words
A channel encoder as claimed in Claim 7, characterized in that the memory circuit comprises a first sub-memory which determines a first partial digital sum value (DS a in response to the even bits of the n-bit information word, a second sub-memory which supplies a second partial digital sum value (DS b ) in response to the odd bits of the n-bit information word, and a third sub-memory which derives said 2-bit word (x a , x b ) from the first and the second partial digital sum value (DS a , DS b ) and the digital sum variation.
Claim 10
Dependent Claim
87 words
A channel encoder as claimed in Claim 8, characterized in that in the first and the second sub-memory there are stored digital sum values (DS a , DS b ) which have been formed by appending each time the 1-bit word x'a, x' b , respectively, having a predetermined value, to said even bits and odd bits, respectively, the combination thus obtained passed the precoder, the last two bits of fixed value of the precedingm-bit code word supplied by the precoder having been applied to the precoder.
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