US4003041A
Expired / Lapsed
US
⏱️ 0.0 years remaining
System for converting binary signals into shorter balanced ternary code signals
Assignee: Individual
•
Filing: 1974-12-30
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Granted: 1977-01-11
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Expires: 1994-12-30
Abstract
Abstract A system for converting multi-unit 1 and 0 bit binary code signals into one less unit multi-unit 0, + and - bit ternary code signals with a D.C. (direct current) component and having the same number of 0-bits or units in each signal. This conversion is accomplished by dividing each binary word code or signal into two groups of units or bits, converting one group to form a balance code with one less unit or bit than the binary code and a constant number of 0-bits, and converting the other part of each binary word for controlling the conversion and distribution of the + and - bits from the 1-bits in the code words of the first group. In the event there are more + bits than - bits or vice versa in a code word, an inverter is provided for inverting the + and - bits in the next word containing the same unbalance of + and - bits, so that any D.C. component produced by such an unbalance in one word will be eliminated or counterbalanced by inverting the next following word with the same unbalance.
Inventors
- 👤 Henrik Cornelis Anthony van Duuren
- 👤 Herman DA Silva
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-24 08:02
CPC Classifications
H; H04; H04L; H04L25/00; H04L25/38; H04L25/40; H04L25/49; H04L25/4917; H04L25/4923; H04L25/4925
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
177 words
A system for converting n-bit binary code signals of more than three bits per signal of 1 and 0 bits into a ternary balanced code signal of n-1 bits of 0, + and - bits per ternary code signal, wherein each ternary signal has the same number of 0-bits, comprising: A. means for dividing each signal of said binary code into two groups of units, the first group consisting of the first n-3 bits of each code signal, B. means for converting said first group of bits into the first n-1 bits having a constant ratio of 0 and 1-bits per signal, C. means for converting the 1-bits of said first group of bits into + and - bits according to the second group of the last 3-bits of each binary code signal, and D. means for inverting the + and - bits in alternate ternary code signals having the same unevenness in the number of + and - bits, so that after a few converted ternary signals any D.C. component in said ternary signals is eliminated.
Claim 2
Independent Claim
177 words
A system for converting n-bit binary code signals of more than three bits per signal of 1 and 0 bits into a ternary balanced code signal of n-1 bits of 0, + and - bits per ternary code signal, wherein each ternary signal has the same number of 0-bits, comprising: A. means for dividing each signal of said binary code into two groups of units, the first group consisting of the first n-3 bits of each code signal, B. means for converting said first group of bits into the first n-1 bits having a constant ratio of 0 and 1-bits per signal, C. means for converting the 1-bits of said first group of bits into + and - bits according to the second group of the last 3-bits of each binary code signal, and D. means for inverting the + and - bits in alternate ternary code signals having the same unevenness in the number of + and - bits, so that after a few converted ternary signals any D.C. component in said ternary signals is eliminated.
Claim 3
Dependent Claim
17 words
A system according to claim 1 wherein said n-bit binary code consists of seven units per signal.
Claim 4
Dependent Claim
17 words
A system according to claim 1 wherein said n-bit binary code consists of eight units per signal.
Claim 5
Dependent Claim
17 words
A system according to claim 1 wherein each of said means for converting includes a shift register.
Claim 6
Dependent Claim
15 words
A system according to claim 1 wherein said means for inverting comprises a flip-flop circuit.
Claim 7
Dependent Claim
37 words
A system according to claim 1 wherein each of said means for converting comprises a relay having a switch and each switch is connected for connection to three different potentials corresponding to 0; +, and - bits.
Claim 8
Dependent Claim
25 words
A system according to claim 1 wherein said inverting means is connected to said means for converting the 1-bits of said first group of bits.
Claim 9
Dependent Claim
34 words
A system according to claim 1 wherein said means for connecting the 1-bits of said first group of bits comprises a converter for the last three bits divided from said 8-bit binary code signal.
Claim 10
Dependent Claim
25 words
A system according to claim 8 wherein said dividing means is connected to said converters for the first group of bits and the three bits.
Claim 11
Dependent Claim
20 words
A system according to claim 8 wherein said inverting means is connected to said converter for the last three bits.
References Cited (Backward Citations)
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US3631463A
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-01-11 | 1980-07-12 | 1981-01-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-01-11 | 1984-07-12 | 1985-01-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-01-11 | 1988-07-12 | 1989-01-11 | $7700.00 | Window Closed / Lapsed |