US5387552A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of fabrication of PNP structure in a common substrate containing NPN or MOS structures
Assignee: National Semiconductor Corp
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Filing: 1992-09-14
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Granted: 1995-02-07
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Expires: 2012-09-14
Abstract
Abstract A pnp device in a BiCMOS structure (1). PNP transistors (4) are fabricated without the need for additional process steps on the same substrate as npn (2), PMOS (8), and NMOS (6) devices. The process not only requires a minimum number of additional process steps, but results in devices with near optimum device characteristics.
Inventors
- 👤 Ali A. Iranmanesh
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 02:09
CPC Classifications
H; H10; H10D; H10D84/00; H10D84/01; H10D84/0107; H10D84/0109; H10D84/02; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S148/00; Y10S148/009
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
164 words
A method of fabricating an integrated circuit device, comprising the steps of: simultaneously implanting p-type dopants into first, second, and third regions of a substrate, said first, second, and third regions forming at least a portion of a buried layer of a pnp transistor, a well region of a NMOS transistor, and a p-type channel stop; forming an epitaxial silicon layer over at least said first and said second regions, a first portion of said epitaxial silicon layer forming a base region of said pnp transistor, a second portion of said epitaxial silicon layer forming a channel region of a PMOS transistor, a third portion of said epitaxial layer forming a channel region of said NMOS transistor, and a fourth portion of said epitaxial layer forming a sink region of said pnp transistor; forming an emitter region in contact with said base region of said pnp transistor; and forming source and drain regions in contact with channel regions of said NMOS and PMOS transistor.
Claim 2
Independent Claim
164 words
A method of fabricating an integrated circuit device, comprising the steps of: simultaneously implanting p-type dopants into first, second, and third regions of a substrate, said first, second, and third regions forming at least a portion of a buried layer of a pnp transistor, a well region of a NMOS transistor, and a p-type channel stop; forming an epitaxial silicon layer over at least said first and said second regions, a first portion of said epitaxial silicon layer forming a base region of said pnp transistor, a second portion of said epitaxial silicon layer forming a channel region of a PMOS transistor, a third portion of said epitaxial layer forming a channel region of said NMOS transistor, and a fourth portion of said epitaxial layer forming a sink region of said pnp transistor; forming an emitter region in contact with said base region of said pnp transistor; and forming source and drain regions in contact with channel regions of said NMOS and PMOS transistor.
Claim 3
Dependent Claim
78 words
The method as recited in claim 1 further comprising the steps of: after said step of forming an epitaxial layer, implanting an n-type dopant into said channel region of said PMOS transistor; and simultaneously implanting a p-type dopant into said channel region of said PMOS transistor, said channel region of said NMOS transistor, and said sink region of said pnp transistor, said step of implanting a p-type dopant setting a threshold voltage of said NMOS and PMOS transistors.
Claim 4
Dependent Claim
57 words
The method as recited in claim 1 further comprising the step of providing additional n-type dopants into a base of said pnp transistor by the steps of: forming a polycrystalline layer on said epitaxial layer; implanting n-type dopants into said polycrystalline layer above said pnp base; and diffusing dopants from said polycrystalline layer into said pnp base.
Claim 5
Dependent Claim
48 words
The method as recited in claim 1 further comprising the step of forming an npn transistor in said substrate and p-type channel stops adjacent said npn transistor, said step of implanting p-type dopants into first, second, and third regions also implanting p-type dopants to form said channel stops.
Claim 6
Dependent Claim
59 words
The method as recited in claim 1 further comprising the step of forming a polycrystalline contact layer on said epitaxial layer, and doping at least a portion of said polycrystalline layer with p-type dopants to form an emitter contact of said pnp transistor, said emitter region of said pnp transistor is formed by diffusing dopants from said emitter contact.
Claim 7
Dependent Claim
49 words
The method as recited in claim 5 further comprising the step of implanting p-type dopants to form heavily doped p-type regions in said epitaxial layer adjacent said emitter of said pnp transistor, ajacent an emitter of an npn transistor, and in source and drain regions of a PMOS transistor.
Claim 8
Dependent Claim
33 words
The method as recited in claim 5 further comprising the steps of: forming oxide sidewalls on contacts in said contact layer; and removing oxide sidewalls from said emitter contact of said pnp transistor.
Claim 9
Dependent Claim
29 words
The method as recited in claim 7 wherein said step of removing oxide sidewalls further comprises the step of removing oxide sidewalls from base contacts of an npn transistor.
Claim 10
Dependent Claim
34 words
The method as recited in claim 5 further comprising the step of implanting-p-type dopants to form doped p-type regions in said epitaxial layer between a first and a second stringer of said emitter contact.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1998-02-06 | 1998-08-08 | 1999-02-07 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2002-02-06 | 2002-08-08 | 2003-02-07 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2006-02-06 | 2006-08-08 | 2007-02-07 | $7700.00 | Window Closed / Lapsed |