Microprocessor with two groups of internal buses

Claim 2

A microprocessor comprising: an arithmetic processing unit; a group of internal memories comprising address translation table means for storing information for translating logic addresses into physical addresses, and cache memory means for storing information for translating logic addresses into physical addresses; internal memory control means for controlling a data input/output operation between external memories and said group of internal memories; a first group of internal buses for connecting said arithmetic processing unit, said group of internal memories and said internal memory control means, and for transferring logical addresses and data between said arithmetic processing unit and said group of internal memories; and a second group of internal buses for connecting said group of internal memories, said internal memory control means and external bus control means, and for transferring physical addresses and data among said group of internal memories and said external memories, each element in said group of internal memories and said internal memory control means being connected to said first group of internal buses and to said second group of internal buses in parallel, and said internal memory control means controlling use of said second group of internal buses, a data input/output operation to said cache memory means, and updating operation of said address translation table means, wherein said internal memory control means is connected between said first group of internal buses and said second group of internal buses and wherein the use of said first group of internal buses is controlled by said arithmetic processing unit, and the use of said second group of internal buses is controlled by said internal memory control means, both of said arithmetic processing unit and said internal memory control means being executed independently.

Claim 3

A microprocessor according to claim 1, wherein said cache memory means comprises a plurality of cache memories, and one internal memory control means is provided for all of said group of internal memories.

Claim 4

A microprocessor according to claim 1, wherein each cache memory in said cache memory means comprises an instruction cache memory and a data cache memory, and is provided with an address translation table, and wherein said instruction cache memory and said data cache memory are connected to said first group of internal buses and said second group of internal buses.

Claim 5

A microprocessor according to claim 1, wherein said arithmetic processing unit, said group of internal memories, said internal memory control means, said external bus control means, said first group of internal buses and said second group of internal buses are provided on one chip.

Claim 6

A microprocessor according to claim 1, wherein said external bus control means receives an instruction provided from said internal memory control means, monitors a writing address when a writing operation for said external memories occurs, and eliminates data stored in said group of internal memories when an address of data in said internal memories is equal to a writing address, and said internal memory control means, said external bus control means, and said arithmetic processing unit operate independently of each other.

Claim 7

A microprocessor according to claim 1, further comprising: write buffer means, incorporated between said first group of internal buses and said second group of internal buses, for temporarily storing data to be transferred between said first group of internal buses and said second group of internal buses.

Claim 8

A microprocessor according to claim 1, wherein data transfer via said first group of internal buses and data transfer via said second group of internal buses are carried out substantially independently of each other.

Claim 9

A microprocessor comprising: a plurality of arithmetic processing units; a plurality of internal memory groups, each comprising address translation tables for storing information for translating logic addresses into physical addresses, and cache memories for storing information for translating logical addresses into physical addresses, each of said internal memory groups being connected to each of said arithmetic processing units; a first group of internal buses for connecting said arithmetic processing units, an internal memory control means and said internal memory groups, and for transferring logical addresses and data among said arithmetic processing units and said internal memory groups; a second group of internal buses for connecting said internal memory groups and said internal memory control means, and for transferring physical addresses and data among said internal memory groups; said internal memory control means for controlling a data access operation through said internal buses, said internal memory control means being connected between said first group of internal buses and said second group of internal buses; each element in said internal memory groups and said internal memory control means being connected to said first group of internal buses and said second group of internal buses in parallel, and said internal memory control means controlling use of said second group of internal buses, a data input/output operation to said cache memories, and updating operation of said address translation tables, and wherein said internal memory control means is connected between said first group of internal buses and said second group of internal buses and wherein the use of said first group of internal buses is controlled by said arithmetic processing unit, and the use of said second group of internal buses is controlled by said internal memory control means, both of said arithmetic processing unit and said internal memory control means being executed independently.

Claim 10

A microprocessor comprising: a plurality of arithmetic processing units; a plurality of internal memory groups, each comprising address translation tables for storing information for translating logic addresses into physical addresses, and cache memories for storing information for translating logical addresses into physical addresses, each of said internal memory groups being connected to each of said arithmetic processing units; a first group of internal buses for connecting said arithmetic processing units, an internal memory control means and said internal memory groups, and for transferring logical addresses and data among said arithmetic processing units and said internal memory groups; a second group of internal buses for connecting said internal memory groups and said internal memory control means, and for transferring physical addresses and data among said internal memory groups; said internal memory control means for controlling a data access operation through said internal buses, said internal memory control means being connected between said first group of internal buses and said second group of internal buses; each element in said internal memory groups and said internal memory control means being connected to said first group of internal buses and said second group of internal buses in parallel, and said internal memory control means controlling use of said second group of internal buses, a data input/output operation to said cache memories, and updating operation of said address translation tables, and wherein said internal memory control means is connected between said first group of internal buses and said second group of internal buses and wherein the use of said first group of internal buses is controlled by said arithmetic processing unit, and the use of said second group of internal buses is controlled by said internal memory control means, both of said arithmetic processing unit and said internal memory control means being executed independently.

Claim 11

A microprocessor according to claim 8, wherein there is one said internal memory control means.

Claim 12

A microprocessor according to claim 8, wherein said microprocessor is formed on one chip.

Claim 13

A microprocessor according to claim 8, wherein data transfer via said first group of internal buses and data transfer via said second group of internal buses are carried out substantially independently of each other.