EP0153779A2
Expired / Lapsed
EP
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Data processing system provided with a memory access controller
Assignee: Koninklijke Philips NV
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Filing: 1985-02-12
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Granted: —
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Expires: 2005-02-12
Abstract
Abstract The data processing system of the invention comprises a processor, a memory access controller and a memory hierarchy. The memory access controller is placed between the processor and the memory hierarchy and controls access thereto. The memory access controller comprises a cache controller and a translation unit which are connected in parallel to an address bus connected to the processor and by which virtual addresses are transported. The memory access controller supports segments which are unit of sharing the memory, each segment is split up into pages. The memory access controller also supports regions which contain at least one segment. The memory access controller further supports sectors, divided into blocks which are other units of sharing the memory. And the memory access controller is also provided for enabling access with I/O units.
Inventors
- 👤 Cecil Hertz Kaplinsky
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-08 13:40
CPC Classifications
G; G06; G06F; G06F12/00; G06F12/02; G06F12/08; G06F12/10; G06F12/1027; G06F12/1045; G06F12/1063
Claims Analysis
Total Claims: 23
Claim 1
Independent Claim
402 words
Data processing system comprising a processor connected to a commun address bus, a memory hierarchy comprising at least a cache memory and a local memory connected to the carmm bus, a memory access controller connected to the cannzn bus and via a cache address bus to the cache memory, which memory access controller comprises: - a cache controller which comprises a first storage unit for storing first indicators which indicate the data present in the cache memory, a first check unit connected to said first storage unit and having a first address input connected to said processcr for receiving virtual addresses supplied by the processor, said first check unit being provided for checking upon a received virtual address if said virtual address corresponds to one of said first indicators stored into the first storage unit and for generating a first check result _ signal upon correspondence and a second check result signal upon non-correspondence, said cache controller being further provided with a first enabling unit for enabling the access to the cache memary, which first enabling unit being activated upon receiving the first check result signal; - a translation unit having a second address input for receiving virtual addresses and being provided for translating virtual addresses into physical addresses, said translation unit comprises a second storage unit for storing second indicators which indicate the data present in the local memory, a second check unit connected to said storage unit and to said second address input and being provided for checking upon a received virtual address if said virtual address corresponds to one of said second indicators stored into the second storage unit and for generating a third check result signal upon correspondence and a fourth check result signal upon non-correspondence, said translation unit being controlled by said second check result signal supplied at a first control input thereof, said translation unit being further provided with a second enabling unit for enabling the access to the local memory, which second enabling unit being activated upon receiving the third check result signal; characterized in that the cache controller by means of his firest address input and the translation unit by means of his second address input being connected in parallel to an address bus which is connected to a virtual address output of the processor, which address bus being provided for transporting the virtual addresses simultaneously to the cache controller and the translation unit.
Claim 2
Dependent Claim
402 words
Data processing system comprising a processor connected to a commun address bus, a memory hierarchy comprising at least a cache memory and a local memory connected to the carmm bus, a memory access controller connected to the cannzn bus and via a cache address bus to the cache memory, which memory access controller comprises: - a cache controller which comprises a first storage unit for storing first indicators which indicate the data present in the cache memory, a first check unit connected to said first storage unit and having a first address input connected to said processcr for receiving virtual addresses supplied by the processor, said first check unit being provided for checking upon a received virtual address if said virtual address corresponds to one of said first indicators stored into the first storage unit and for generating a first check result _ signal upon correspondence and a second check result signal upon non-correspondence, said cache controller being further provided with a first enabling unit for enabling the access to the cache memary, which first enabling unit being activated upon receiving the first check result signal; - a translation unit having a second address input for receiving virtual addresses and being provided for translating virtual addresses into physical addresses, said translation unit comprises a second storage unit for storing second indicators which indicate the data present in the local memory, a second check unit connected to said storage unit and to said second address input and being provided for checking upon a received virtual address if said virtual address corresponds to one of said second indicators stored into the second storage unit and for generating a third check result signal upon correspondence and a fourth check result signal upon non-correspondence, said translation unit being controlled by said second check result signal supplied at a first control input thereof, said translation unit being further provided with a second enabling unit for enabling the access to the local memory, which second enabling unit being activated upon receiving the third check result signal; characterized in that the cache controller by means of his firest address input and the translation unit by means of his second address input being connected in parallel to an address bus which is connected to a virtual address output of the processor, which address bus being provided for transporting the virtual addresses simultaneously to the cache controller and the translation unit.
Claim 3
Dependent Claim
66 words
Data processing system as claimed in Claim 1, characterized in that the memory access controller comprises a microcontroller which comprises a bus access signal generator connected to said second check unit and being provided for generating upon receiving the fourth check result signal a bus access signal in order to acquire access to the commun bus, said bus access signal generator being connected to said processor.
Claim 4
Dependent Claim
89 words
Data processing system as claimed in Claim 2, characterized in that said memory hierarchy further comprises a main memory, and wherein the microcontroller comprises a second control input for receiving a bus access right generated by the processor upon reception of a bus access signal, said microcontroller further comprises a mapping unit connected to the address bus and provided for translating virtual addresses into map-addresses for addressing the main memory, said microcontroller also comprises third enabling-means far generating an enable signal in order to access to the main memory.
Claim 5
Dependent Claim
71 words
Data processing system as claimed in Claim 3, characterized in that said translation unit being provided with first loading means, having a third control input for receiving said enable signal and being provided for loading data fetched from said main memory into said local memory under control of said enable signal, and for loading a second indicator into said second storage unit which indicates the data loaded into the local memory.
Claim 6
Dependent Claim
35 words
Data processing system as claimed in any preceding Claim, characterized in that said first check unit and said first storage unit being formed by a content addressable memory which is connected to the address bus.
Claim 7
Dependent Claim
35 words
Data processing system as claimed in any preceding Claim, characterized in that said second check unit and said secoond storage unit being formed by a content addressable memory which is connected to the address bus.
Claim 8
Dependent Claim
89 words
Data processing system as claimed in any preceding Claim, characterized in that said memory hierarchy further comprises a main memory, said main memory being partitioned into a first number of sectors and said cache memory being partitioned into a second number of sectors, said virtual address comrising a first field indicating a sector number of a sector in said cache memory, said first checking unit being provided for fetching said first field out of said virtual address and for realizing said checking upon the content of said first field.
Claim 9
Dependent Claim
115 words
Data processing system as claimed in Claim 7, characterized in that said sectors of the main memory and the cache memory being partitioned into a third respectively a fourth number of blocks, said virtual address comprising a second field indicating a block number of a block in said cache memory, said first storage unit comprises a presence bit memory for the storage of presence bits indicating the blocks present in the cache memory, said first cheking unit being provided for fetching said second field out of said virtual address and for realizing said checking by controlling if the presence bit of the block number indicated in said field is set in said presence bit memory.
Claim 10
Dependent Claim
62 words
Data processing system as claimed in Claim 8, wherein said cache controller being provided with second loading means for loading data from said main memory into said cache memory, characterized in that said second loading means being provided for loading said data block-wise into said cache memory and for setting the presence bit for the loaded block into said presence bit memory.
Claim 11
Dependent Claim
89 words
Data processing system as claimed in any of the Claims 1 to 6, characterized in that the memory access controller comprises register means connected to said address bus for partitioning the virtual address space occupied by the virtual addresses into a number of different regions and for providing a region number to each region obtained, said register means having a set input for enabling a programmable length of the regions to be partitioned, said register means being provided for realizing said partitioning upon the address bits of virtual addresses.
Claim 12
Dependent Claim
112 words
Data processing system as claimed in any of the Claim 1 to 6, characterized in that said local memory being partitionable into a variable number of segments, each of the segments being partitionable into fixed length pages, said virtual address comprising a segment number for indicating the number of a segment and a page number field for indicating the number of a page within a segment indicated by the segment number field, said memory access controller further comprising a segment table pointer register for storing descriptors of the segments present in the local memory, each of said descriptors comprising a segment table pointer for indicating a segment table of the local memory.
Claim 13
Dependent Claim
17 words
Data processing system as claimed in Claim 11, characterized int hat said segments having a variable length.
Claim 14
Dependent Claim
20 words
Data processing system as claimed in Claim 10 and 11, characterized in that each region comprises at least one segment.
Claim 15
Dependent Claim
60 words
Data processing system as claimed in Claim 13, characterized in that said register means comprises for each region partitioned a register pair, said register pair comprises a segment table pointer register for storing references about the areas of the virtual address space accessible to a current process, and a segment table length register for indicating the length of the segment.
Claim 16
Dependent Claim
116 words
Data processing system as claimed in Claim 3 and 14, characterized in that said mapping unit has a first input connected to said register means for receiving region numbers and a second input connected to said-segment table pointer register for receiving segment table pointer indications indicating the segment table for said region number in the local memory, said mapping unit being provided for generating a physical address by using the segment number field of the virtual address as an index for indicating a position in said segment table and by using the page number field as an index for indicating a position in a page table register indicated by the indexed position in said segment table.
Claim 17
Dependent Claim
38 words
Data processing system as claimed in Claim 11, 12, 13, 14 or 15, characterized in that said descriptors comprise a protection field for indicating whether or not the access to the segment indexed by the descriptor is protected.
Claim 18
Dependent Claim
41 words
Data processing system as claimed in Claim 14, 15 or 16, characterized in that segment table pointer register comprises a location for storing a protection indication in order to indicate whether or not the access to the indexed region is protected.
Claim 19
Dependent Claim
30 words
Data processing system as claimed in Claim 16, characterized in that said descriptors comprise a non-cacheable bit for prohibiting if setted that a segment is loaded into the cache memory.
Claim 20
Dependent Claim
31 words
Data processing system as claimed in Claim 16, characterized in that said descriptor comprises a local bit for forcing if setted that a segment to be loaded in the local memory.
Claim 21
Dependent Claim
35 words
Data processing system as claimed in Claim 16, characterized in that said page table comprises a dirty bit for indicating that said pages has been readed and/or written into the cache memory and/or local memory.
Claim 22
Dependent Claim
51 words
Data processing system as claimed in any preceding Claim, characterized in that the memory access controller is connected to an I/O unit by means of the address bus, said memory access controller comprises a further mapping unit for mapping a received virtual address into a physical address for the I/O unit.
Claim 23
Dependent Claim
36 words
Memory access controller to be used in a data processing system as claimed in any of the preceding Claims, characterized in that said memory access controller ctxnprises a cache controller, a translation unit and a microcontroller.
References Cited (Backward Citations)
No citation records indexed.
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