US5097413A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Abort circuitry for microprocessor
Assignee: Individual
•
Filing: 1990-01-17
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Granted: 1992-03-17
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Expires: 2010-01-17
Abstract
Abstract An abort circuit for a microprocessor includes a circuit receiving and latching an external abort signal to produce an internal abort signal, and circuitry responsive to the internal abort signal for preventing register transfer circuitry from responding to register transfer signals during execution of a current instruction that would otherwise result in modifying information in internal non-addressable programmable registers during duration of the internal abort signal, and abort reset circuity for responding to a reset signal to cause the abort input circuitry to stop producing the internal abort signal at the end of the abort condition.
Inventors
- 👤 William D. Mensch, Jr.
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 20:09
CPC Classifications
G; G06; G06F; G06F9/00; G06F9/06; G06F9/30; G06F9/30181; G06F9/30185; G06F9/3017; G06F9/30174; G06F15/00; G06F15/76; G06F15/78; G06F15/7828; G06F15/7832; G06F9/30189; G06F9/38; G06F9/3861
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
227 words
In a chip including a microprocessor containing a plurality of internal non-addressable registers which are programmable in response to instructions of a program, register transfer means response to register transfer signals for effectuating transfer of information between said registers and a data bus and/or an address bus on said chip, and instruction decoding means for decoding the instructions to produce the register transfer signals, an abort circuit in the microprocessor comprising: (a) abort input means for receiving an external abort signal indicative of an abort condition and latching said external abort signal to produce an internal abort signal, said microprocessor including address output buffer means for latching address information; (b) first means for conducting said internal abort signal to said register transfer means; (c) second means responsive to said internal abort signal for preventing said register transfer means from responding to register transfer signals during execution of a current instruction that otherwise would result in modifying information in said programmable registers during the duration of said internal abort signal; (d) abort vector generating means responsive to said internal abort signal for loading an abort vector address of an abort subroutine into said address output buffer means; and (e) abort reset means for responding to a reset signal to cause said abort input means to stop producing said internal abort signal at the end of said abort condition.
Claim 2
Dependent Claim
227 words
In a chip including a microprocessor containing a plurality of internal non-addressable registers which are programmable in response to instructions of a program, register transfer means response to register transfer signals for effectuating transfer of information between said registers and a data bus and/or an address bus on said chip, and instruction decoding means for decoding the instructions to produce the register transfer signals, an abort circuit in the microprocessor comprising: (a) abort input means for receiving an external abort signal indicative of an abort condition and latching said external abort signal to produce an internal abort signal, said microprocessor including address output buffer means for latching address information; (b) first means for conducting said internal abort signal to said register transfer means; (c) second means responsive to said internal abort signal for preventing said register transfer means from responding to register transfer signals during execution of a current instruction that otherwise would result in modifying information in said programmable registers during the duration of said internal abort signal; (d) abort vector generating means responsive to said internal abort signal for loading an abort vector address of an abort subroutine into said address output buffer means; and (e) abort reset means for responding to a reset signal to cause said abort input means to stop producing said internal abort signal at the end of said abort condition.
Claim 3
Dependent Claim
36 words
The abort circuit in said microprocessor chip as recited in claim 1 wherein said plurality of programmable registers include an index register, a stack register, an accumulator register, a status register, and a program counter register.
Claim 4
Dependent Claim
35 words
The abort circuitry in said microprocessor chip as recited in claim 2 wherein said plurality of programmable registers include all registers of said chip that are programmable by a programmer and include no incrementing circuits.
Claim 5
Independent Claim
200 words
A method of operating a microprocessor in a chip, the microprocessor including a plurality of internal non-addressable registers which are programmable in response to instructions of a program, register transfer means responsive to register transfer signals for effectuating transfer of information between said registers and a data bus and/or an address bus on said chip, address output buffer means for latching address information, and instruction decoding means for decoding the instructions to produce the register transfer signals, the method comprising the steps of: (a) receiving an external abort signal indicative of an abort condition and latching said external abort signal to produce an internal abort signal; (b) conducting said internal abort signal to said register transfer means; (c) preventing said register transfer means from responding to register transfer signals during execution of a current instruction that otherwise would result in modifying information in said programmable registers during the duration of said internal abort signal; (d) loading an abort vector address into said address output buffer means in response to said internal abort signal; and (e) responding to a reset signal to cause said abort input means to stop producing said internal abort signal at the end of said abort condition.
Claim 6
Independent Claim
200 words
A method of operating a microprocessor in a chip, the microprocessor including a plurality of internal non-addressable registers which are programmable in response to instructions of a program, register transfer means responsive to register transfer signals for effectuating transfer of information between said registers and a data bus and/or an address bus on said chip, address output buffer means for latching address information, and instruction decoding means for decoding the instructions to produce the register transfer signals, the method comprising the steps of: (a) receiving an external abort signal indicative of an abort condition and latching said external abort signal to produce an internal abort signal; (b) conducting said internal abort signal to said register transfer means; (c) preventing said register transfer means from responding to register transfer signals during execution of a current instruction that otherwise would result in modifying information in said programmable registers during the duration of said internal abort signal; (d) loading an abort vector address into said address output buffer means in response to said internal abort signal; and (e) responding to a reset signal to cause said abort input means to stop producing said internal abort signal at the end of said abort condition.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-03-17 | 1995-09-16 | 1996-03-17 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-03-17 | 1999-09-16 | 2000-03-17 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-03-17 | 2003-09-16 | 2004-03-17 | $7700.00 | Window Closed / Lapsed |