Single chip MOS computer with expandable memory

Claim 2

An MOS digital computer comprising, on a single silicon substrate: a bidirectional data bus, said bus having terminals for coupling to external circuit means; a random-access memory (RAM) coupled to said data bus; a central processing unit (CPU) for performing arithmetic functions and for controlling the operation of said computer, said CPU coupled to said data bus and to said RAM; a read-only memory (ROM) for storing bytes of program, said ROM coupled to said data bus and to said CPU; said CPU including a program counter means, coupled to said ROM and said data bus for providing address signals to said ROM when said counter means contains a count which is less than a predetermined count, and for providing address signals to external memory when said counter means contains a count which exceeds said predetermined count; input detection means for receiving first and second externally applied predetermined signals for testing of said computer and for providing control signals to said program counter means and said ROM, said control signals for causing coupling of instructions from such external memory to said data bus independent of the count contained within said counter means when said first predetermined signal is received by said input detection means, and for causing said ROM to be coupled to said data bus such that said program stored in said ROM may be externally examined when said second predetermined signal is received by said input detection means; whereby the program storage capacity of said computer may be expanded by use of external memory which is automatically addressed by signals from said program counter means, and whereby said ROM and CPU may be separately tested.

Claim 3

The computer defined in claim 1 wherein said ROM is a programmable read-only memory (PROM).

Claim 4

The computer defined by claim 1 wherein said predetermined count approximately equals the maximum number of bytes which may be stored in said ROM.

Claim 5

The computer defined by claim 3 wherein said input detection means comprises a voltage level detection means for detecting three logic states on a single line.

Claim 6

The computer defined by claim 1 wherein said computer is fabricated entirely of n-channel devices.

Claim 7

The computer defined by claim 5 wherein said n-channel devices include polycrystalline silicon gates.

Claim 8

An MOS digital computer comprising, on a single substrate: a data bus; a read-only memory (ROM) for storing bytes of program storage, coupled to said data bus; a program counter for addressing said ROM, coupled to said ROM and to said data bus; a central processing unit (CPU) for interpreting instructions from said ROM and for executing said instructions, said CPU including an arithmetic logic means for performing arithmetic operations, said CPU being coupled to said data bus; a random-access memory (RAM) for storing digital signals coupled to said data bus; said computer including a RAM address register coupled to said RAM, said RAM address register receiving an input address from a multiplexing means, said multiplexing means coupled to select a first address bus, or a second address bus, said first address bus being coupled to receive an address corresponding to a location in said RAM from said data bus, said first address bus also being coupled to circuit means which selectively provides predetermined signals to said first address bus to selectively shift said RAM location; said second address bus coupled to a stack pointer register for providing address signals for locations in said RAM for storage of the contents of said program counter, said stack pointer register automatically incrementing or decrementing said address signals for locations in said RAM for said contents of said program counter; said computer including a third address bus coupled to said multiplexing means and to said RAM such that an address stored in said ROM may be used to select a location in said RAM; whereby directly addressable locations in said RAM may be addressed when said locations are storing data since said circuit means causes data to be stored in other locations and whereby said RAM is used to store said contents of said program counter with said stack pointer register automatically providing address signals.

Claim 9

An MOS digital computer comprising, on a single substrate: a data bus; a read-only memory (ROM) for storing bytes of program storage, coupled to said data bus; a program counter for addressing said ROM, coupled to said ROM and to said data bus; a central processing unit (CPU) for interpreting instructions from said ROM and for executing said instructions, said CPU including an arithmetic logic means for performing arithmetic operations, said CPU being coupled to said data bus; a random-access memory (RAM) for storing digital signals coupled to said data bus; said computer including a RAM address register coupled to said RAM, said RAM address register receiving an input address from a multiplexing means, said multiplexing means coupled to select a first address bus, or a second address bus, said first address bus being coupled to receive an address corresponding to a location in said RAM from said data bus, said first address bus also being coupled to circuit means which selectively provides predetermined signals to said first address bus to selectively shift said RAM location; said second address bus coupled to a stack pointer register for providing address signals for locations in said RAM for storage of the contents of said program counter, said stack pointer register automatically incrementing or decrementing said address signals for locations in said RAM for said contents of said program counter; said computer including a third address bus coupled to said multiplexing means and to said RAM such that an address stored in said ROM may be used to select a location in said RAM; whereby directly addressable locations in said RAM may be addressed when said locations are storing data since said circuit means causes data to be stored in other locations and whereby said RAM is used to store said contents of said program counter with said stack pointer register automatically providing address signals.

Claim 10

The computer defined by claim 7 wherein said ROM is a programmable read-only memory.

Claim 11

The computer defined by claim 7 wherein said circuit means includes a bistable circuit for providing said location, said bistable circuit coupled to said first address bus.

Claim 12

The computer defined by claim 9 wherein said stack pointer register includes means for adding a binary one to the address on said second address bus whereby said contents of said program counter may be stored in adjacent locations within said RAM.

Claim 13

The computer defined by claim 10 wherein said RAM comprises a static RAM.

Claim 14

The computer defined by claim 10 wherein said computer is fabricated entirely of n-channel devices.

Claim 15

The computer defined by claim 12 wherein said n-channel devices include polycrystalline silicon gates.