US3962683A
Expired / Lapsed
US
⏱️ 0.0 years remaining
CPU programmable control system
Assignee: Individual
•
Filing: 1973-09-04
•
Granted: 1976-06-08
•
Expires: 1993-09-04
Abstract
Abstract A synchronous computing system includes a central processor unit interconnected with external memory units. The processor is integrated monolithically on a single chip and includes a plurality of data registers, a parallel arithmetic logic unit and an instruction register interconnected by a common parallel buss. A control section of the processor synchronizes internal operation of the processor and also system operation, and includes a plurality of programmable logic arrays to provide a versatile method of accommodating different instruction sets, sequences of operation, and instruction cycle duration. The arrays reduce the number of interconnects required and increases utilization of semiconductor material for forming active devices. This is a continuation of application Ser. No. 176,665, filed Aug. 31, 1971, now abandoned.
Inventors
- 👤 Max Brown
- 👤 Gary Boone
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 20:18
CPC Classifications
G; G06; G06F; G06F7/00; G06F7/38; G06F7/48; G06F7/50; G06F7/501; G06F13/00; G06F13/14; G06F13/16; G06F13/18; G06F13/38; G06F13/42; G06F13/4204; G06F13/4234; G06F13/4243; G06F9/00; G06F9/06; G06F9/22; G06F9/223; G06F2207/00; G06F2207/38; G06F2207/3804; G06F2207/386; G06F2207/3872
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
204 words
In a synchronous CPU characterized by an operation cycle having a first subcycle during which the CPU may access an external memory and a second subcycle during which the CPU processes data and instructions retrieved from memory, a control system comprising: a. circuit means for generating said first and second subcycle times, said circuit means including a programmable logic array for selectively defining the time duration of said subcycles, b. instruction decode means for receiving instructions from said external memory and for producing output signals corresponding to the processor operation required for respective instructions, said decode means comprising a programmable logic array for selectively defining processor operation resulting from selected instructions, c. cycle timing means operably connected to said circuit means, and having inputs coupled to said instruction decode means to receive output signals therefrom, for controlling the number of processor cycles required for respective instructions. and d. timing control means for receiving inputs from said circuit means, and coupled to said decode means to receive output signals therefrom, and receiving inputs from the cycle timing means, for generating control signals to synchronize processor operation, said timing control means including a programmable logic array for selectively defining a sequence of operation of the processor.
Claim 2
Dependent Claim
204 words
In a synchronous CPU characterized by an operation cycle having a first subcycle during which the CPU may access an external memory and a second subcycle during which the CPU processes data and instructions retrieved from memory, a control system comprising: a. circuit means for generating said first and second subcycle times, said circuit means including a programmable logic array for selectively defining the time duration of said subcycles, b. instruction decode means for receiving instructions from said external memory and for producing output signals corresponding to the processor operation required for respective instructions, said decode means comprising a programmable logic array for selectively defining processor operation resulting from selected instructions, c. cycle timing means operably connected to said circuit means, and having inputs coupled to said instruction decode means to receive output signals therefrom, for controlling the number of processor cycles required for respective instructions. and d. timing control means for receiving inputs from said circuit means, and coupled to said decode means to receive output signals therefrom, and receiving inputs from the cycle timing means, for generating control signals to synchronize processor operation, said timing control means including a programmable logic array for selectively defining a sequence of operation of the processor.
Claim 3
Dependent Claim
66 words
A control system for a synchronous central processor unit as set forth in claim 1 including status decode means for determining the status of arithmetic operations performed by said processor by sampling the logic level of selected bits in the accumulator of said processor, said status decode means including a programmable logic array for selectively defining which bits of an instruction enable a status decode operation.
Claim 4
Dependent Claim
176 words
A control section of a synchronous central processor unit, said central processor unit having an accumulator register, and being connected to an external memory, said control section comprising: a state timer circuit for generating a first portion of a cycle of operation only during which can the processor access said external memory, and a second portion of the cycle during which the processor operates on the data retrieved from said external memory, an instruction decode circuit for generating processor control signals responsive to respective instructions the processor can execute, a cycle timer connected to said instruction decode circuit and operative to control the number of cycles required for a selected instruction, a timing control circuit for synchronizing operation of the processor, a status decode circuit for determining the status of the accumulator register of the processor following an arithmetic operation, said state timer circuit including a first programmable logic array; and b. means for selectively defining the gates of said array to control the duration of said first and second portions of said processor operating cycle.
Claim 5
Dependent Claim
176 words
A control section of a synchronous central processor unit, said central processor unit having an accumulator register, and being connected to an external memory, said control section comprising: a state timer circuit for generating a first portion of a cycle of operation only during which can the processor access said external memory, and a second portion of the cycle during which the processor operates on the data retrieved from said external memory, an instruction decode circuit for generating processor control signals responsive to respective instructions the processor can execute, a cycle timer connected to said instruction decode circuit and operative to control the number of cycles required for a selected instruction, a timing control circuit for synchronizing operation of the processor, a status decode circuit for determining the status of the accumulator register of the processor following an arithmetic operation, said state timer circuit including a first programmable logic array; and b. means for selectively defining the gates of said array to control the duration of said first and second portions of said processor operating cycle.
Claim 6
Dependent Claim
42 words
Apparatus as set forth in claim 3 wherein: said instruction decode circuit includes a second programmable array; and means for selectively defining the gates of said second array to selectively control the output signals generated in response to a given instruction code.
Claim 7
Dependent Claim
52 words
A method for fabricating the control section of a synchronous processor as set forth in claim 4 including: said cycle timer circuit includes a third programmable logic array; and means for selectively defining the gates of said third array to control the number of processor cycles required for a given instruction code.
Claim 8
Dependent Claim
49 words
A method for fabricating the control section of a synchronous processor as set forth in claim 5 including: said timing control circuit includes a fourth programmable logic array; and means for selectively defining the gates of said fourth array to control the sequences of operation of said synchronous processor.
Claim 9
Dependent Claim
55 words
A method for fabricating the control section of a synchronous processor as set forth in claim 6 wherein: said status decode circuit includes a fifth programmable logic array; and means for selectively defining the gates of said fifth array to control which bits of an instruction are utilized to enable a status decode operation. pg,107
Claim 10
Dependent Claim
25 words
Apparatus as set forth in claim 7 wherein forming said first, second, third, fourth, and fifth programmable logic arrays are formed on a single chip.
References Cited (Backward Citations)
US3453607A
Cited
US3537074A
Cited
US3564507A
Cited
US3528060A
Cited
US3602900A
Cited
US3566368A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1979-06-08 | 1979-12-08 | 1980-06-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1983-06-08 | 1983-12-08 | 1984-06-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1987-06-08 | 1987-12-08 | 1988-06-08 | $7700.00 | Window Closed / Lapsed |