Expandable data storage for a calculator system

Claim 1

In a calculator system of the type implemented on first and second sets of semiconductor chips with the first set of semiconductor chips having keyboard input means for entering data and functions, a plurality of separate data memory locations for storing in bit-parallel format a plurality of multi-digit words of coded information, wherein the data memory locations comprise addressable memory means, addressable storage means for storing a plurality of program instructions for controlling the operation of the calculator system, control means for receiving the program instructions and generating control connections according thereto, parallel arithmetic logic means connected to the control means and to the data memory locations for performing parallel arithmetic and logic operations on the multi-digit coded words from the data memory locations one digit at a time, multi-digit display means connected to the data memory locations for displaying the numerical results of calculations made by the calculator system, timing means for producing timing signals for strobing the keyborad input means and the display means during a scan cycle, status output means for sending status information indicative of operating condition of the calculator system and data output means for outputting first and second data words from said data memory locations, a data register chip of the second set of chips operatively responsive to said first set for providing auxiliary data storage capacity comprising in combination: a. input means on the data register chip responsive to said status information for generating first and second operations signals and a synchronization signal; b. storage means on the data register chip coupled to said data output means for storing a first multi-digit data word transmitted from said first set indicative of an input/output operation command and further indicative of the particular register to be addressed among a set of registers in the data register chip; c. register storage means on the data register chip addressable for inputting or outputting data in accordance with said first and second operations signals, including a set of individually addressable registers; d. register timing means on the data register chip for driving said set of registers in timed relationship with said timing signals in said first set of chips in response to said synchronization signal; e. first decode means on the data register chip responsive to said first data word for selectively addressing at least one of the set of registers of said register storage means; and f. input delay means coupling said storage means to said data output means for communicating a first set of digits of a second data word to the selected one of the set of registers sequentially without delay and for communicating at least one other digit of said second data word to said selected one of the registers after a preselected delay.