Bus error recognition for microprogrammed data processor

Claim 1

A microprocessor for communicating with equipment peripheral thereto over a bus during a bus cycle, said microprocessor comprising: a control unit for generating bus logic control signals indicative of how said bus cycle is to be run; latch means coupled to said control unit for latching said bus logic control signals; bus control logic means coupled to said latch means and to said bus, for running said bus cycle, including generating bus control signals via said bus for controlling the use of said bus by said peripheral equipment, in response to said latched bus logic control signals; and bus error logic means coupled to said bus and to said bus control logic means, said bus error logic means including first means for receiving a first signal from said peripheral equipment indicating that an error has occurred during said bus cycle; second means for receiving a second signal from said peripheral equipment indicating that said bus cycle should be rerun; and third means for forcing said bus control logic means to rerun said bus cycle using said latched bus logic control signals, including generating said bus control signals via said bus for controlling the use of said bus by said peripheral equipment, only in response to said first and said second signals being simultaneously received by said first and second means; whereby said bus cycle will not be rerun if said peripheral equipment provides only said first or second signal.