US4045661A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Apparatus for detecting and processing errors
Assignee: Bull SAS
•
Filing: 1975-04-23
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Granted: 1977-08-30
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Expires: 1995-04-23
Abstract
Abstract The disclosure describes apparatus for handling detected errors in a data processing system. First means define and locate the detected errors and second means allow the attempted reexecution of the instruction being executed when the error is detected.
Inventors
- 👤 Pierre Gabriel Antoine
- 👤 Jean-Claude Marcel Cassonnet
- 👤 Daniel Rene Vinot
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:26
CPC Classifications
G; G06; G06F; G06F11/00; G06F11/07; G06F11/14; G06F11/1402; G06F11/1405; G06F11/141
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
98 words
In a data processing system comprising a central processor including functional devices capable of executing instructions stored in a memory, and means for detecting errors, improved apparatus for handling the detected error, comprising: a first register having a plurality of bit locations, each of said functional devices being connected to one of said bit locations so as to permit the location and detection of errors; and a second register operatively connected to selected of said functional devices, which are subject to several types of error for determining in which of said functional devices the detected error has occurred.
Claim 2
Dependent Claim
98 words
In a data processing system comprising a central processor including functional devices capable of executing instructions stored in a memory, and means for detecting errors, improved apparatus for handling the detected error, comprising: a first register having a plurality of bit locations, each of said functional devices being connected to one of said bit locations so as to permit the location and detection of errors; and a second register operatively connected to selected of said functional devices, which are subject to several types of error for determining in which of said functional devices the detected error has occurred.
Claim 3
Dependent Claim
66 words
Apparatus according to claim 1, further comprising a control mask register including first binary means for indicating whether said central processor is in a machine error state, second binary means for indicating whether the detected error has been corrected, and gate means for allowing said system to be locked by indicating whether the detected error was detected while said central processor was in a transistory mode.
Claim 4
Dependent Claim
68 words
Apparatus according to claim 1, further comprising: means responsive to a detected hardware error for locking said first register so that other errors will be masked, and means responsive to the type of error detected for inhibiting said central processor until at least one of the following events has occurred: a diagnostic processor has been actuated, isolated routine tests are carried out, or the detected error is ignored.
References Cited (Backward Citations)
US3533065A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1980-08-29 | 1981-02-28 | 1981-08-30 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1984-08-29 | 1985-02-28 | 1985-08-30 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1988-08-29 | 1989-02-28 | 1989-08-30 | $7700.00 | Window Closed / Lapsed |