Fast asynchronous resource master-slave combination

Claim 1

In a data processing system, the combination comprising: memory means for storing data; a plurality of data resource means for supplying and utilizing data; system bus means for transferring data between the memory means and the data resource means; a plurality of bus master controller means for controlling access to the system bus means by the data resource means, each bus master controller means further comprising clock means, independent of any other clock means employed in the system, for supplying local timing signals for use only in and by the respective means of its associated bus master controller means, bus control master means for coupling a data resource means to the system bus means, bus request means responsive to the bus control master means for supplying a control request signal indicating access to the system bus means is required, select means for receiving a bus grant signal representing access to the system bus means is granted, passing means responsive to the bus request means and to the select means for outputting the bus grant signal if the bus controller means did not supply a control request signal as gated solely by signals from the clock means, and bus control slave means responsive to the bus control master means for coupling the system bus means to the memory means and responsive to the bus request means and to the select means for controlling the system bus means in response to a bus grant signal if the bus controller means supplied a control request signal; means for coupling the bus request means together to a single bus, which bus will carry bus request signals from any of the bus request means; means for coupling the passing means of each bus master controller means to the select means of a successive bus controller means, the select means of a first one of said bus master controller means being coupled to receive a bus grant signal from the utilizing means; signal means in the bus control slave means for supplying a completion signal indicating a data transfer is completed; and termination means in the bus control master means responsive to the clock means and to the signal means for retaining control of the system bus until the bus master controller means has reached a predetermined state.