US4148011A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Asynchronous priority circuit for controlling access to a bus
Assignee: General Automation Inc
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Filing: 1977-06-06
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Granted: 1979-04-03
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Expires: 1997-06-06
Abstract
Abstract A priority arbitration circuit for resolving priority between a plurality of master devices which compete for access to one or more slave devices over a common bus. All master devices share a common Request line and a common Busy line. Priority is passed along serially from one device to another in sequence until all pending requests have been serviced, after which priority reverts to an initial device. The first device to issue a request gains priority. Simultaneous requests are resolved in the order in which the devices are connected in the priority chain. A device having a local request and receiving priority on the priority chain sets the Busy signal to lock out all other devices.
Inventors
- 👤 Angus McLagan
- 👤 Kirk B. Cummings
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-23 12:00
CPC Classifications
G; G06; G06F; G06F13/00; G06F13/14; G06F13/36; G06F13/368; G06F13/37
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
277 words
In a modular digital data processing system wherein a plurality of master devices communicate with a plurality of slave devices over a common bus, apparatus for resolving priority among the master devices when more than one is seeking access to the bus, comprising: a priority circuit in each device, first and second control conductors connected to each of said circuits, priority conductor means connecting the priority circuits in series starting with a first master device and terminating at a last master device in sequence, means in each device for initiating a local access request signal when access to the bus is required, means responsive to said initiating means for applying a request signal on the first control conductor to each of the priority circuits indicating a request has been initiated, each priority circuit including means responsive to the request signal on the first control conductor and a priority signal received on the priority conductor means from the previous device in the series for generating a control signal, said means generating the control signal including clock means for providing a predetermined fixed delay between the time the request signal on the first control line and the priority signal on the priority conductor are received and the time the control signal indicates they have been received, means responsive to the delayed control signal for sending a priority signal to the next device in series after said predetermined delay, and means responsive to the local request signal and the delayed control signal for applying a busy signal to the second control conductor when a local request is present and the delayed control signal indicates the priority signal has been received.
Claim 2
Dependent Claim
277 words
In a modular digital data processing system wherein a plurality of master devices communicate with a plurality of slave devices over a common bus, apparatus for resolving priority among the master devices when more than one is seeking access to the bus, comprising: a priority circuit in each device, first and second control conductors connected to each of said circuits, priority conductor means connecting the priority circuits in series starting with a first master device and terminating at a last master device in sequence, means in each device for initiating a local access request signal when access to the bus is required, means responsive to said initiating means for applying a request signal on the first control conductor to each of the priority circuits indicating a request has been initiated, each priority circuit including means responsive to the request signal on the first control conductor and a priority signal received on the priority conductor means from the previous device in the series for generating a control signal, said means generating the control signal including clock means for providing a predetermined fixed delay between the time the request signal on the first control line and the priority signal on the priority conductor are received and the time the control signal indicates they have been received, means responsive to the delayed control signal for sending a priority signal to the next device in series after said predetermined delay, and means responsive to the local request signal and the delayed control signal for applying a busy signal to the second control conductor when a local request is present and the delayed control signal indicates the priority signal has been received.
Claim 3
Dependent Claim
44 words
Apparatus of claim 1 further including means in each priority circuit responsive to the presence of a request signal on the first control conductor for inhibiting said means from initiating a local access request while the request signal remains on the first control conductor.
Claim 4
Dependent Claim
38 words
Apparatus of claim 2 wherein each priority circuit further includes means responsive to the presence of a busy signal on the second control conductor for inhibiting said means from applying a busy signal to the second control conductor.
Claim 5
Dependent Claim
42 words
Apparatus of claim 3 wherein each priority circuit further includes means inhibiting said means sending a priority signal to the next device when a local request is present and a busy signal is present from another priority circuit on the second conductor.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1982-04-02 | 1982-10-02 | 1983-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1986-04-02 | 1986-10-02 | 1987-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1990-04-02 | 1990-10-02 | 1991-04-03 | $7700.00 | Window Closed / Lapsed |