Asynchronous priority circuit for controlling access to a bus

Claim 1

In a modular digital data processing system wherein a plurality of master devices communicate with a plurality of slave devices over a common bus, apparatus for resolving priority among the master devices when more than one is seeking access to the bus, comprising: a priority circuit in each device, first and second control conductors connected to each of said circuits, priority conductor means connecting the priority circuits in series starting with a first master device and terminating at a last master device in sequence, means in each device for initiating a local access request signal when access to the bus is required, means responsive to said initiating means for applying a request signal on the first control conductor to each of the priority circuits indicating a request has been initiated, each priority circuit including means responsive to the request signal on the first control conductor and a priority signal received on the priority conductor means from the previous device in the series for generating a control signal, said means generating the control signal including clock means for providing a predetermined fixed delay between the time the request signal on the first control line and the priority signal on the priority conductor are received and the time the control signal indicates they have been received, means responsive to the delayed control signal for sending a priority signal to the next device in series after said predetermined delay, and means responsive to the local request signal and the delayed control signal for applying a busy signal to the second control conductor when a local request is present and the delayed control signal indicates the priority signal has been received.