Single-channel bus system for multi-master use with bit cell synchronization, and master station comprising a bit cell synchronization element suitable for this purpose

Claim 2

A single-channel bus system for multi-master use for a plurality of mutually asynchronously controlled master stations using messages comprising an arbitration field of a uniform number of bit cells of fixed nominal length, followed by a data field, the system comprising: (a) a bus having a dominant state and a non-dominant state, and (b) for each respective master station: a storage element for storing an intended delay time between a local signal transition generated by the respective master station and a resultant detectable signal transition, which resultant detectable signal transition results from the local signal transition and is detectable on the bus; sequencer means, having a cycle duration which corresponds to said nominal length, for starting an arbitration field bit cell when the sequencer means reaches a given state within a cycle; a first adjusting element (148) for presetting said sequencer means with the contents of the storage element under control of a state transition, on the bus, to the dominant bus state; wherein (c) at least one master station comprises a second adjusting element (140) for loading a current state of said sequencer means into said storage element during the data field of a message to be transmitted by the respective master station, under control of a further state transition, on the bus, to the dominant bus state.

Claim 3

The system of claim 1, wherein: (a) the storage element is a register having a plurality of parallel outputs and a plurality of parallel inputs; and (b) the sequencer means is a counter having (i) a plurality of parallel inputs coupled with the parallel outputs of the register; (ii) a maximum count which corresponds to the cycle duration; (iii) a current counting position of the counter which is the current state of the sequencer means; and (iv) a plurality of parallel outputs coupled with the parallel inputs of the register.

Claim 4

A master station for use in a bus-system along with at least one other master station, the master stations in the bus-system being mutually asynchronously controlled using messages comprising an arbitration field of a uniform number of bit cells of fixed nominal length, followed by a data field, the bus-system further including a bus having a dominant state and a non-dominant state, the claimed master station comprising: (a) a storage element for storing an intended delay time, which intended delay time represents a delay between a local signal transition generated by the respective master station and a resultant detectable signal transition, which resultant detectable signal transition results from the local signal transition and is detectable on the bus; (b) sequencer means, having a cycle duration which corresponds to said nominal length, for starting an arbitration field bit cell when the sequencer means reaches a given state within a cycle; (c) a first adjusting element (148) for presetting said sequencer means with the contents of the storage element under control of a station transition, on the bus, to the dominant bus state; and (d) a second adjusting element (140) for loading a current state of said sequencer means into said storage element during the data field of a message to be transmitted by the master station, under control of a further state transition, on the bus, to the dominant bus state.

Claim 5

The master station of claim 3 wherein (a) the storage element has a plurality of parallel outputs and a plurality of parallel inputs; and (b) the sequencer means is a counter having (i) a plurality of parallel inputs coupled with the parallel outputs of the storage element; (ii) a maximum count which corresponds to the cycle duration; (iii) a current counting position of the counter which is the current state of the sequencer means; and (iv) a plurality of parallel outputs coupled with the parallel inputs of the storage element.

Claim 6

The master station of claim 3 wherein the storage element is a register.

Claim 7

The master station of claim 3 wherein (a) the master station is adaptable to assume a slave state; and (b) the sequencer means is presettable with the contents of the storage element, under the control of a state transition, on the bus, to the dominant bus state.

Claim 8

Apparatus for synchronizing a master station with at least one other master station in a single-channel multi-master bus-system, the bus-system including a bus having a first and second state, the apparatus comprising: (a) means for transmitting and receiving bits to and from the bus, the bits having a fixed nominal length; (b) means for storing an anticipated delay time between a local signal transition generated by the master station and a resultant detectable signal transition, which resultant detectable signal transition results from the local signal transition and is detectable on the bus; (c) means for creating a cycle, having a duration which corresponds to said fixed nominal length, and for starting transmission by the master station of a bit of a first type at a given state within the cycle; (d) means for presetting said cycle creating means with contents of the storing means, under control of a state transition between the first and second states on the bus; and (e) means for loading a current state, of the cycle creating means, into the storing means during transmission by the master station of a bit of a second type under control of a further state transition between the first and second states on the bus.

Claim 9

Apparatus for synchronizing a master station with at least one other master station in a single-channel multi-master bus-system, the bus-system including a bus having a first and second state, the apparatus comprising: (a) means for transmitting and receiving bits to and from the bus, the bits having a fixed nominal length; (b) means for storing an anticipated delay time between a local signal transition generated by the master station and a resultant detectable signal transition, which resultant detectable signal transition results from the local signal transition and is detectable on the bus; (c) means for creating a cycle, having a duration which corresponds to said fixed nominal length, and for starting transmission by the master station of a bit of a first type at a given state within the cycle; (d) means for presetting said cycle creating means with contents of the storing means, under control of a state transition between the first and second states on the bus; and (e) means for loading a current state, of the cycle creating means, into the storing means during transmission by the master station of a bit of a second type under control of a further state transition between the first and second states on the bus.