Output precharge circuit for memory

Claim 2

A memory integrated circuit comprising: a network of memory cells to store information elements; a bit line, coupled to the network, to communicate the information elements; an output pad, coupled to the bit line, receiving and outputting the information elements; an output amplifier, coupled to the bit line and the output pad, selectively providing the information elements from the bit line to the output pad; and means, coupled to the output amplifier, for precharging the output amplifier during a precharging phase to a predetermined voltage before a reading phase during which an information element is provided to the output pad, wherein the predetermined voltage is substantially equal to an intermediate voltage between a high logic level and a low logic level of the output pad, wherein said means for precharging includes means for selectively forcing one of a charging transistor and a discharging transistor, both connected to said output pad, to a conductive state, in response to the state of the information element prior to said precharging phase.

Claim 3

An integrated circuit as claimed in claim 1 wherein the high logic level is substantially equal to 5 volts and the intermediate voltage is substantially within the range of 1 to 2 volts.

Claim 4

An integrated circuit as claimed in claim 2 wherein the intermediate voltage is substantially equal to 1.4 volts.

Claim 5

An integrated circuit as claimed in claim 1 wherein the output amplifier includes said charging transistor and said discharging transistor connected in series, both transistors being coupled to the output pad.

Claim 6

An integrated circuit as claimed in claim 4 further comprising means, coupled to the charging transistor and the discharging transistor, for controlling conduction of the transistors, the means for controlling including means for forcing the charging transistor into a conductive state and for forcing the discharging transistor into an off state when an information element provided by the bit line corresponds substantially to the high logic level, and means for forcing the discharging transistor to a conductive state and forcing the charging transistor to an off state when an information element provided by the bit line corresponds substantially to the low logic level.

Claim 7

A memory integrated circuit comprising: a network of memory cells to store information elements; a bit line, coupled to the network, to communicate the information elements; an output pad, coupled to the bit line, receiving and outputting the information elements; an output amplifier, coupled to the bit line and the output pad, selectively providing the information elements from the bit line to the output pad, wherein said output amplifier includes: a charging transistor and a discharging transistor connected in series, both transistors being coupled to the output pad, and means, coupled to the transistors, for controlling conduction of the transistors, such that the charging transistor is forced into a conductive state and the discharging transistor is forced into an off state when an information element provided by the bit line corresponds substantially to a high logic level, and the discharging transistor is forced into a conductive state and the charging transistors is forced into an off state when an information element provided by the bit line corresponds substantially to a low logic level; means, coupled to the output amplifier, for precharging the output amplifier during a precharging phase to a predetermined voltage before a reading phase during which an information element is provided to the output pad, wherein the predetermined voltage is substantially equal to an intermediate voltage between a high logic level and a low logic level of the output pad; and a memorizing circuit, coupled to the output pad and to the means for controlling conduction, storing, during the precharging phase, a logic level present at the output pad during a previous reading phase, and prohibiting conduction of one of the charging or discharging transistors.

Claim 8

A memory integrated circuit comprising: a network of memory cells to store information elements; a bit line, coupled to the network, to communicate the information elements; an output pad, coupled to the bit line, receiving and outputting the information elements; an output amplifier, coupled to the bit line and the output pad, selectively providing the information elements from the bit line to the output pad, wherein said output amplifier includes: a charging transistor and a discharging transistor connected in series, both transistors being coupled to the output pad, and means, coupled to the transistors, for controlling conduction of the transistors, such that the charging transistor is forced into a conductive state and the discharging transistor is forced into an off state when an information element provided by the bit line corresponds substantially to a high logic level, and the discharging transistor is forced into a conductive state and the charging transistors is forced into an off state when an information element provided by the bit line corresponds substantially to a low logic level; means, coupled to the output amplifier, for precharging the output amplifier during a precharging phase to a predetermined voltage before a reading phase during which an information element is provided to the output pad, wherein the predetermined voltage is substantially equal to an intermediate voltage between a high logic level and a low logic level of the output pad; and a memorizing circuit, coupled to the output pad and to the means for controlling conduction, storing, during the precharging phase, a logic level present at the output pad during a previous reading phase, and prohibiting conduction of one of the charging or discharging transistors.

Claim 9

An integrated circuit as claimed in claim 6 wherein: the means for forcing the charging transistor to a conductive state includes a first logic gate coupled to the charging transistor; the means for forcing the discharging transistor to a conductive state includes a second logic gate coupled to the discharging transistor; and the memorizing circuit is coupled to the first and second logic gates.

Claim 10

An integrated circuit as claimed in claim 7 further comprising a threshold inverter having an input and an output, the input of the threshold inverter coupled to the output pad and the output of the threshold inverter coupled to the first and second logic gates.

Claim 11

An integrated circuit as claimed in claim 7 wherein the first logic gate includes a NAND gate and the second logic gate includes a NOR gate, both gates receive, during the reading phase, a logic signal representing an information element provided by the bit line.

Claim 12

An integrated circuit as claimed in claim 9 wherein the NAND gate and the NOR gate each have a first input and a second input, the first input of each gate receiving, during the precharging phase, an output of the memorizing circuit and the second input of each gate receiving, during the precharging phase, the output of the threshold inverter.

Claim 13

An integrated circuit as claimed in claim 7 further comprising a first threshold inverter coupled between the output pad and the first logic gate and a second threshold inverter coupled between the output pad and the second logic gate.

Claim 14

An integrated circuit as claimed in claim 7 further comprising at least one hold circuit coupled between the bit line and the first and second logic gates, to maintain information elements read from the memory cells at the logic gates.

Claim 15

A memory integrated circuit comprising: a network of memory cells to store information elements; a bit line, coupled to the network, to communicate the information elements; an output pad, coupled to the bit line, receiving and outputting the information elements; an output amplifier, coupled to the bit line and the output pad, selectively providing the information elements from the bit line to the output pad; and a precharging circuit, coupled to the output amplifier, precharging the output amplifier during a precharging phase to a predetermined voltage before a reading phase, wherein the predetermined voltage is substantially equal to an intermediate voltage between a high logic level and a low logic level of the output pad, by selectively forcing one of a charging transistor and a discharging transistor, both connected to said output pad, to a conductive state, in response to the state of the information element prior to said precharging phase.

Claim 16

A memory integrated circuit comprising: a network of memory cells to store information elements; a bit line, coupled to the network, to communicate the information elements; an output pad, coupled to the bit line, receiving and outputting the information elements; an output amplifier, coupled to the bit line and the output pad, selectively providing the information elements from the bit line to the output pad; and a precharging circuit, coupled to the output amplifier, precharging the output amplifier during a precharging phase to a predetermined voltage before a reading phase, wherein the predetermined voltage is substantially equal to an intermediate voltage between a high logic level and a low logic level of the output pad, by selectively forcing one of a charging transistor and a discharging transistor, both connected to said output pad, to a conductive state, in response to the state of the information element prior to said precharging phase.

Claim 17

An integrated circuit as claimed in claim 13 wherein the high logic level is substantially equal to 5 volts and the intermediate voltage is substantially within the range of 1 to 2 volts.

Claim 18

An integrated circuit as claimed in claim 14 wherein the intermediate voltage is substantially equal to 1.4 volts.

Claim 19

An integrated circuit as claimed in claim 15 wherein the output amplifier includes said charging transistor and said discharging transistor connected in series, both transistors being coupled to the output pad.

Claim 20

An integrated circuit as claimed in claim 16 wherein the output amplifier further includes at least one logic gate to force the charging transistor to a conductive state and the discharging transistor to an off state when an information element provided by the bit line corresponds to the high logic level and to force the discharging transistor to a conductive state and the charging transistor to an off state when an information element provided by the bit line corresponds to the low logic level.

Claim 21

A memory integrated circuit comprising: a network of memory cells to store information elements; a bit line, coupled to the network, to communicate the information elements; an output pad, coupled to the bit line, receiving and outputting the information elements; an output amplifier, coupled to the bit line and the output pad, selectively providing the information elements from the bit line to the output pad, wherein said output amplifier includes: a charging transistor and a discharging transistor connected in series, both transistors being coupled to the output pad, and at least one logic gate to force the charging transistor to a conductive state and the discharging transistor to an off state when an information element provided by the bit line corresponds to a high logic level and to force the discharging transistor to a conductive state when an information element provided by the bit line corresponds to a low logic level; a precharging circuit, coupled to the output amplifier, precharging the output amplifier during a precharging phase to a predetermined voltage before a reading phase, wherein the predetermined voltage is substantially equal to an intermediate voltage between a high logic level and a low logic level of the output pad; and a memorizing circuit, coupled to the output pad, to store, during the precharging phase, a logic level present at the output pad during a previous reading phase.

Claim 22

A memory integrated circuit comprising: a network of memory cells to store information elements; a bit line, coupled to the network, to communicate the information elements; an output pad, coupled to the bit line, receiving and outputting the information elements; an output amplifier, coupled to the bit line and the output pad, selectively providing the information elements from the bit line to the output pad, wherein said output amplifier includes: a charging transistor and a discharging transistor connected in series, both transistors being coupled to the output pad, and at least one logic gate to force the charging transistor to a conductive state and the discharging transistor to an off state when an information element provided by the bit line corresponds to a high logic level and to force the discharging transistor to a conductive state when an information element provided by the bit line corresponds to a low logic level; a precharging circuit, coupled to the output amplifier, precharging the output amplifier during a precharging phase to a predetermined voltage before a reading phase, wherein the predetermined voltage is substantially equal to an intermediate voltage between a high logic level and a low logic level of the output pad; and a memorizing circuit, coupled to the output pad, to store, during the precharging phase, a logic level present at the output pad during a previous reading phase.

Claim 23

An integrated circuit as claimed in claim 18 further comprising a threshold inverter having an input and an output, wherein the input of the threshold inverter is coupled to the output pad and the output of the threshold inverter is coupled to the logic gates to control operation of the transistors.

Claim 26

A method as claimed in claim 20 wherein the step of storing includes the step of storing information elements in a network of memory cells and the step of selectively providing includes the step of communicating information elements along a bit line.