EP0319223A2
Expired / Lapsed
EP
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An output circuit system of static random access memory circuit
Assignee: Panasonic Holdings Corp
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Filing: 1988-11-28
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Granted: —
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Expires: 2008-11-28
Abstract
Abstract The invention relates to an output circuit system of static random access memory, which is designed to set the output potential of the data output circuit to an intermediate potential by detecting the transition of the address signal before the data in a memory cell is read out from the memory cell, and then, the output potential of the data output circuit is changed from the intermediate voltage to H level or from the intermediate potential to L level. In this way, since the output potential changes from the intermediate potential to H level or L level, the transition time of the output potential is shortened, and therefore the data reading action may be increased in speed. Ath the same time, the momentary current through the data output circuit may be decreased.
Inventors
- 👤 Hiroaki Okuyama
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-09 04:08
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C11/40; G11C11/41; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 5
Claim 1
Independent Claim
231 words
An output circuit system of static random access memory comprising: a memory cell block containing plural memory cells; output control means for receiving internal data changed depending on the data in any one of said plural memory cells selected by an address signal; data output means composed of P-channel and N-channel MOS FETs of which sources are connected to two supply potentials, in which an output signal of said output control means is applied to gates of said P-channel and N-channel MOS FETs for on/off control, and an output potential at a connection point of drains of said P-channel and N-channel MOS FETs is changed to a potential level corresponding to a data in said selected memory cell; and intermediate potential setting means for setting said output potential of said data output means to an intermediate potential between an immediately preceding output potential of said data output means and one of said supply potentials, after a transition of said address signal and before change of said internal data, on the basis of said transition of said address signal and said output potential of said data output means, in which said output control means changes said output potential of said data output means from said intermediate potential to a potential corresponding to a data in said selected memory cell, after transition of said address signal and after change of said internal data.
Claim 2
Dependent Claim
231 words
An output circuit system of static random access memory comprising: a memory cell block containing plural memory cells; output control means for receiving internal data changed depending on the data in any one of said plural memory cells selected by an address signal; data output means composed of P-channel and N-channel MOS FETs of which sources are connected to two supply potentials, in which an output signal of said output control means is applied to gates of said P-channel and N-channel MOS FETs for on/off control, and an output potential at a connection point of drains of said P-channel and N-channel MOS FETs is changed to a potential level corresponding to a data in said selected memory cell; and intermediate potential setting means for setting said output potential of said data output means to an intermediate potential between an immediately preceding output potential of said data output means and one of said supply potentials, after a transition of said address signal and before change of said internal data, on the basis of said transition of said address signal and said output potential of said data output means, in which said output control means changes said output potential of said data output means from said intermediate potential to a potential corresponding to a data in said selected memory cell, after transition of said address signal and after change of said internal data.
Claim 3
Dependent Claim
69 words
An output circuit system of static random access memory according to claim 1, wherein internal data converting means for detecting the transition of said address signal and changing said internal data to L level or H level for a specific period is disposed at an input side of said output control means, and an output of said internal data converting means is supplied to said intermediate potential setting means.
Claim 4
Dependent Claim
35 words
An output circuit system of static random access memory according to claim 1, wherein an electric signal generated by detection of transition of said address signal is directly applied into said intermediate potential setting circuit.
Claim 5
Dependent Claim
208 words
An output circuit system of static random access memory according to claim 1, wherein said intermediate potential setting circuit is comprising: first swtiching means connected between a gate of one of MOS FETs of said data output means and a first supply potential of lower potential; and second switching means connected between a gate of the other one of MOS FETs of said data output means and a second supply potential of higher potential, in which when said address signal transits while the output potential of said data output means is in H level state, said second switching means becomes into active state in order to activate the other one of MOS FETs of said data output means, and an output potential of said data output means is set at an intermediate potential between the H level and said first supply potential, and when said address signal transits while the output potential of said data output means is in L level state, said first switching means becomes into active state in order to activate said one of MOS FETs of said data output means, and an output potential of said data output means is set at an intermediate potential between the L level and said second supply potential.
References Cited (Backward Citations)
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