EP0471289A1
Expired / Lapsed
EP
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High speed output buffer unit preliminarily shifting output voltage level
Assignee: NEC Corp
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Filing: 1991-08-08
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Granted: —
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Expires: 2011-08-08
Abstract
Abstract An output buffer unit comprises a controlling circuit (31 a) responsive to an input data signal (DB) for producing a first controlling signal and a driving circuit (31 b) implemented by a series combination of a p-channel type field effect transistor (2a) and an n-channel type field effect transistor (2b) complementarily shifted between one and off states for producing an output data signal, and a shifting circuit (31 e) is provided in association with the driving circuit so as to transfer a second controlling signal produced from the previous output data signal stored in a latching circuit (31d) to the field effect transistors (2a/2b) for preliminarily changing the voltage level of an output data signal and, thereafter, to transfer the first controlling signal to the field effect transistors (2a/2b) for finally determining the voltage level of the next output data signal so that the voltage level at the output node of the driving circuit quickly crosses over a discriminating level of data bit.
Inventors
- 👤 Hiroyuki c/o NEC Corporation Goto
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 15:21
CPC Classifications
H; H03; H03K; H03K19/00; G; G11; G11C; G11C7/00; G11C7/10; G11C7/1048; G11C7/1051; H03K19/01; H03K19/017; H03K19/01728
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
214 words
An output buffer unit comprising a) a controlling circuit (31 a; 41 a) responsive to an input signal (DB) for forming a first controlling signal, and b) a driving circuit (31 b; 41 b) implemented by a series combination of a first transistor (2a) of a first channel conductivity type and a second transistor (2b) of a second channel conductivity type opposite to said first channel conductivity type, said first and second transistors being complementarily shifted between on and off states for producing an output signal at an output node (2c) between said first and second transistors, characterized by c) a latching circuit (31d; 41d) operative to temporarily store a previous output signal supplied from said output node and producing a second controlling signal, and d) a shifting circuit (31e; 41e) having a first input port coupled to said controlling circuit, a second input port coupled to said latching circuit and an output port coupled to said first and second transistors, and responsive to a timing signal (PS) for transferring said second controlling signal to said first and second transistors in a first phase of operation, said shifting circuit being operative to supply said first controlling signal to said first and second transistors in a second phase of operation next to said first phase.
Claim 2
Dependent Claim
214 words
An output buffer unit comprising a) a controlling circuit (31 a; 41 a) responsive to an input signal (DB) for forming a first controlling signal, and b) a driving circuit (31 b; 41 b) implemented by a series combination of a first transistor (2a) of a first channel conductivity type and a second transistor (2b) of a second channel conductivity type opposite to said first channel conductivity type, said first and second transistors being complementarily shifted between on and off states for producing an output signal at an output node (2c) between said first and second transistors, characterized by c) a latching circuit (31d; 41d) operative to temporarily store a previous output signal supplied from said output node and producing a second controlling signal, and d) a shifting circuit (31e; 41e) having a first input port coupled to said controlling circuit, a second input port coupled to said latching circuit and an output port coupled to said first and second transistors, and responsive to a timing signal (PS) for transferring said second controlling signal to said first and second transistors in a first phase of operation, said shifting circuit being operative to supply said first controlling signal to said first and second transistors in a second phase of operation next to said first phase.
Claim 3
Dependent Claim
35 words
An output buffer unit as set forth in claim 1, in which said first controlling signal is opposite in logic level to said input signal and identical in logic level to said second controlling signal.
Claim 4
Dependent Claim
64 words
An output buffer unit as set forth in claim 1 or 2, in which said latching circuit (31d) comprises first inverting circuits (31 da/31 db) arranged in a flip-flop configuration, and second inverting circuits (31dc/31dd) coupled in parallel to the output node of said flip-flop configuration, said second controlling signal taking place at the output nodes of said second inverting circuits (31 dc/31 dd).
Claim 5
Dependent Claim
78 words
An output buffer unit as set forth in any of claims 1 to 3, in which said shifting circuit (31e) comprises first transfer gate means (31ea/31eb) coupled between said controlling circuit (31 a) and said driving circuit (31 b), and second transfer gate means (31 ec/31 ed) coupled between said latching circuit (31 d) and said driving circuit (31 b), said timing signal (PS) complementarily shifting said first and second transfer gate means between on and off states.
Claim 6
Dependent Claim
159 words
An output buffer unit as set forth in any of claims 1 to 4, in which said controlling circuit (41a) comprises a three-state NAND gate (41 aa) responsive to said input signal (DB), and a three-state NOR gate (41 ab) responsive to said input signal (DB), said three-state NAND gate in an active state and said three-state NOR gate in an active state producing said first controlling signal, and in which said latching circuit (41 d) comprises fourth inverting circuits (31 da/31 db) arranged in a flip-flop configuration, and three-state fifth inverting circuits (41da/41db) coupled in parallel to the output node of said flip-flop configuration, said second controlling signal taking place at the output nodes of said three-state fifth inverting circuits in an active state, said shifting circuit (41e) being implemented by said three-state NAND gate, said three-state NOR gate and said three-state fifth inverting circuits selectively controlled between said active states and high-impedance states by said timing signal.
References Cited (Backward Citations)
EP0121217A2
Cited
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