EP0121217A2
Expired / Lapsed
EP
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Output buffer circuit
Assignee: Toshiba Corp
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Filing: 1984-03-27
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Granted: —
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Expires: 2004-03-27
Abstract
Abstract An output buffer circuit has a data input terminal (IN) which receives logic data, load and drive transistors (20,22), a driver (24) for selectively turning on the transistors (20, 22) in accordance with the logic value of the logic data, a data output terminal (OUT) which is connected to a power source terminal (VD) of the VDD level through a current path of the load transistor (20) and is grounded through a current path of the drive transistor (22), and a capacitor (26) connected as a load to the data output terminal (OUT). The output buffer circuit further has a transition detector circuit (46) for generating a pulse signal in responseto a change in level of each of address signals (A1 - AN), and a preset circuit (48) for supplying, in response to the pulse signal, a charge or discharge current to the capacitor (26) while a voltage at the data output terminal (OUT) is not at the VDD/2 level.
Inventors
- 👤 Hiroshi Yasuda
- 👤 Kiyofumi Ochii
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-04 17:11
CPC Classifications
G; G11; G11C; G11C7/00; G11C7/10; G11C7/1051; G11C7/1057; G11C7/106; H; H03; H03K; H03K19/00; H03K19/01; H03K19/017; H03K19/01707; H03K19/01721
Claims Analysis
Total Claims: 14
Claim 1
Independent Claim
264 words
An output buffer circuit comprising: first and second power source terminals (VD, GROUND) of which the potentials are respectively set at first and second levels, a data input terminal (IN) for receiving logic data, a data output terminal (OUT), capacitive means (26) which is connected to said data output terminal (OUT), a first transistor (20) whose current path is connected between said first power source terminal (VD) and said data output terminal (OUT), a second transistor (22) whose current path is connected between said data output terminal (OUT) and said second power source terminal (GROUND), drive circuit (24) for controlling the conduction states of said first and second transistors (20, 22) in accordance with the logic value of said logic data, characterized by further comprising signal generating means (46) for generating a pulse signal, a preset circuit (48) which has first and second switching means (50, 52) and selectively supplies, in response to the pulse signal from said signal generating means (46), one of charge current and discharge current with respect to said capacitive means (26) through said first or second switching means (50, 52) to set the potential of said data output terminal (OUT) at a predetermined level between said first and second levels, and said first and second switching means (50, 52) being turned off when the potential of said data output terminal (OUT) is set at said predetermined level said drive circuit (24) which controls the conduction state of said first and second transistors (20, 22) after the potential of said data output terminal (OUT) is set at the predetermined level.
Claim 2
Dependent Claim
264 words
An output buffer circuit comprising: first and second power source terminals (VD, GROUND) of which the potentials are respectively set at first and second levels, a data input terminal (IN) for receiving logic data, a data output terminal (OUT), capacitive means (26) which is connected to said data output terminal (OUT), a first transistor (20) whose current path is connected between said first power source terminal (VD) and said data output terminal (OUT), a second transistor (22) whose current path is connected between said data output terminal (OUT) and said second power source terminal (GROUND), drive circuit (24) for controlling the conduction states of said first and second transistors (20, 22) in accordance with the logic value of said logic data, characterized by further comprising signal generating means (46) for generating a pulse signal, a preset circuit (48) which has first and second switching means (50, 52) and selectively supplies, in response to the pulse signal from said signal generating means (46), one of charge current and discharge current with respect to said capacitive means (26) through said first or second switching means (50, 52) to set the potential of said data output terminal (OUT) at a predetermined level between said first and second levels, and said first and second switching means (50, 52) being turned off when the potential of said data output terminal (OUT) is set at said predetermined level said drive circuit (24) which controls the conduction state of said first and second transistors (20, 22) after the potential of said data output terminal (OUT) is set at the predetermined level.
Claim 3
Dependent Claim
35 words
An output buffer circuit according to claim 1, characterized in that said signal generating means includes a transition detector circuit (46) for generating the pulse signal in response to the change of an input signal.
Claim 4
Dependent Claim
50 words
An output buffer circuit according to claim 2, characterized in that said transition detector circuit (46) generates the pulse signal having a predetermined pulse width which is not shorter than the period for said preset circuit to change the potential of said data output terminal (IN) to said predetermined level.
Claim 5
Dependent Claim
65 words
An output buffer circuit according to claim 3, characterized in that said transition detector circuit includes delay means (58 to 61) for delaying said input signal, and an exclusive OR gate circuit (56) having a first input terminal to which said input signal is directly supplied and a second input terminal to which said input signal is supplied through said delay means (58 to 61).
Claim 6
Dependent Claim
57 words
An output buffer circuit according to claim 4, characterized in that said preset circuit (48) includes driving means (54) which turn on one of said first and second switching means (50, 52) in accordance with the potential level at said data output terminal (OUT) and in response to the pulse signal from said transition detector circuit (46).
Claim 7
Dependent Claim
147 words
An output buffer circuit according to claim 5, characterized in that said first switching means (50, 52) is an n-channel MOS transistor (50) whose current path is connected between said first power source terminal (VD) and said data output terminal (OUT) and which is rendered conductive as long as the potential of said data output terminal (OUT) is at a level lower than said predetermined level while said n-channel MOS transistor (50) is being driven by said driving means (54), and second switching means is a p-channel MOS transistor (52) whose current path is connected between said data output terminal (OUT) and said second power source terminal (GROUND) and which is rendered conductive as long as the potential of said data output terminal (OUT) is at a level higher than said predetermined level while said p-channel MOS transistor (52) is being deriven by said driving means (54).
Claim 8
Dependent Claim
60 words
An output buffer circuit according to claim 6, characterized in that said driving means has a line connected between the output terminal of said transition detector circuit and the gate of said n-channel MOS transistor (50), and an inverter (54) connected between the output terminal of said transition detector circuit (46) and the gate of said p-channel MOS transistor (52).
Claim 9
Dependent Claim
86 words
An output buffer circuit according to claim 7, characterized in that said drive circuit (24).includes a selector section (32, 34, 36, 38, 40) which makes one of said first and second transistors (20, 22) conductive in accordance with the logic value of said logic data, and which makes each of said first and second transistors (20, 22) nonconductive, regardless of the logic value of said logic data during a period corresponding to the predetermined pulse width of said pulse signal from said transition detector circuit (46).
Claim 10
Dependent Claim
120 words
An output buffer circuit according to claim 8, characterized in that said first transistor (20) is of p-channel MOS type; said second transistor (22) is of n-channel MOS type; said selector section has a second inverter (40), a first OR gate circuit (32, 36) whose first and second input terminals are respectively connected to said data input terminal (IN) and the output terminal of said transition detector circuit (46) and whose output terminal is connected to a gate of said first transistor (20); and an AND gate circuit (34, 38) whose second and first input terminals are respectively connected to the output terminal of said transition detector circuit (46) through said second inverter (40) and said data input terminal (IN).
Claim 11
Dependent Claim
33 words
An output buffer circuit according to claim 9, characterized in that said drive circuit (24) includes a latch section (28, 30) for holding said logic data supplied from said data input terminal (IN).
Claim 12
Dependent Claim
75 words
An output buffer circuit according to claim 10, characterized in that said drive circuit (24) includes a second OR gate circuit (63) through which the output terminal of said transition detector circuit (46) is connected to the second input of said first OR gate circuit (63) and the input terminal of said second inverter (40), second OR gate circuit receives a control signal in addition to the pulse signal from said transition detector circuit (46).
Claim 13
Dependent Claim
57 words
An output buffer circuit according to claim 1, characterized in that said preset circuit (48) includes driving means (54) which turn on one of said first and second switching means (50, 52) in accordance with the potential level at said data output terminal (OUT) and in response to the pulse signal from said signal generating means (46).
Claim 14
Dependent Claim
147 words
An output buffer circuit according to claim 12, characterized in that said first switching means (50, 52) is an n-channel MOS transistor (50) whose current path is connected between said first power source terminal (VD) and said data output terminal and which is rendered conductive as long as the potential of said data output terminal (OUT) is at a level lower than said predetermined level while said n-channel MOS transistor (50) is being driven by said driving means (54), and said second switching means is a p-channel MOS transistor (52) whose current path is connected between said data output terminal (OUT) and said second power source terminal (GROUND) and which is rendered conductive as long as the potential of said data output terminal (OUT) is at a level higher than said predetermined level while said p-channel MOS transistor (52) is being driven by said driving means (54).
References Cited (Backward Citations)
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