Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
298 words
A level-shifting static random access memory cell which may be coupled to a bit line and a word line operating at a first set of high and low logic-state voltages substantially equal to a first power-supply rail potential and a second power-supply rail potential, respectively, said level-shifting static random access memory cell having at least one output node operating at a second set of high and low logic state voltages substantially equal to a third high-voltage power-supply rail potential and said second power-supply rail potential, respectively, said cell comprising: a first P-Channel MOS transistor having a source connected to said third high-voltage power-supply rail potential, and further having a drain and a gate; a first N-Channel MOS transistor having a drain connected to the drain of said first P-Channel MOS transistor, a gate connected to said first power-supply rail potential, and a source; a second N-Channel MOS transistor having a drain connected to the source of said first N-Channel MOS transistor, a source connected to said second power-supply rail potential, and a gate; a second P-Channel MOS transistor having a source connected to said third high-voltage power-supply rail potential, and further having a drain connected to the gate of said first P-Channel MOS transistor and a gate connected to to the drain of said first P-Channel MOS transistor; a third N-Channel MOS transistor having a drain connected to the drain of said second P-Channel MOS transistor, a gate connected to said first power-supply rail potential, and a source connected to the gate of said second N-Channel MOS transistor; a fourth N-Channel MOS transistor having a drain connected to the source of said third N-Channel MOS transistor, a source connected to said second power-supply rail potential, and a gate connected to the source of said first N-Channel MOS transistor.
Claim 2
Dependent Claim
298 words
A level-shifting static random access memory cell which may be coupled to a bit line and a word line operating at a first set of high and low logic-state voltages substantially equal to a first power-supply rail potential and a second power-supply rail potential, respectively, said level-shifting static random access memory cell having at least one output node operating at a second set of high and low logic state voltages substantially equal to a third high-voltage power-supply rail potential and said second power-supply rail potential, respectively, said cell comprising: a first P-Channel MOS transistor having a source connected to said third high-voltage power-supply rail potential, and further having a drain and a gate; a first N-Channel MOS transistor having a drain connected to the drain of said first P-Channel MOS transistor, a gate connected to said first power-supply rail potential, and a source; a second N-Channel MOS transistor having a drain connected to the source of said first N-Channel MOS transistor, a source connected to said second power-supply rail potential, and a gate; a second P-Channel MOS transistor having a source connected to said third high-voltage power-supply rail potential, and further having a drain connected to the gate of said first P-Channel MOS transistor and a gate connected to to the drain of said first P-Channel MOS transistor; a third N-Channel MOS transistor having a drain connected to the drain of said second P-Channel MOS transistor, a gate connected to said first power-supply rail potential, and a source connected to the gate of said second N-Channel MOS transistor; a fourth N-Channel MOS transistor having a drain connected to the source of said third N-Channel MOS transistor, a source connected to said second power-supply rail potential, and a gate connected to the source of said first N-Channel MOS transistor.
Claim 3
Dependent Claim
45 words
The level-shifting static random access memory cell of claim 1, further including a fifth N-Channel MOS transistor having a source connected to said bit line, a drain connected to the drain of said second N-Channel MOS transistor and a gate connected to said word line.
Claim 4
Dependent Claim
41 words
The level-shifting static random access memory cell of claim 1 wherein said first power-supply rail potential is about 5 volts, said second power-supply rail potential is about zero volts, and said third power-supply rail potential is between 8 and 20 volts.