Memory cell with non-volatile memory elements

Claim 2

A memory circuit having non-volatile memory cells each with a bistable circuit including a couple of series each connected in such a way that first and second insulated gates transistors of the first channel type and a third gate transistor of the second channel type are connected in series fashion, a common connection part is provided commonly connecting the gates of the first and third insulated gate transistors, a control signal is applied to the gate of the second insulated gate transistor through a control signal line, separate from said common part, and an output part is provided which is a connection part connecting the first or third insulating gate transistor and the second insulated gate transistor, the connection part of one of the series circuit being connected to the output part of the other series circuit while the output part of the former, to the connection part of the latter, wherein a non-volatile memory element is connected to the connection part of said first and second insulated gate transistors of one of said series circuits.

Claim 3

A memory circuit according to claim 1, in which said non-volatile memory element is a MNOS type device.

Claim 4

A memory circuit according to claim 1, in which said non-volatile memory element is a MAOS type device.

Claim 5

A memory circuit according to claim 1, in which said non-volatile memory element is a floating gate type device.

Claim 6

A memory circuit according to claim 1, in which said first channel is a N-channel and said second channel is a P-channel.

Claim 7

A memory circuit according to claim 1, in which said first channel is a P-type channel and said second channel is a N-type channel.

Claim 8

A memory circuit according to claim 1, wherein the gate electrode of said non-volatile memory element is connected to a non-volatile memory control signal line, separate from said common concentration part and said control signal line.

Claim 9

A memory circuit according to claim 1, wherein the voltage applied to said series circuits is less than the voltage applied to the non-volatile memory element.

Claim 10

A memory circuit comprising: a memory array having unit memory cells arranged in a matrix fashion, said each unit memory cell having a bistable circuit including a couple of series circuits each memory cells each having a bistable circuit including a couple of series circuits each connected in such a way that first and second insulated gate transistors of the first channel type and a third insulated gate transistor of the second channel type are connected in series fashion, a common connection part is provided commonly connecting the gates of the first and third insulated gate transistors, a control signal is applied to the gate of the second insulated gate transistor through a control signal line separate from said common connection part, and an output part is provided which is a connection part connecting the first or third insulating gate transistor and the second insulated gate transistor, the connection part of one of the series circuit being connected to the output part of the other series circuit while the output part of the former, to the connection part of the latter, a non-volatile memory element connected to the connection part of the first and second insulated gate transistors of one of the series circuits, and first and second select transistors respectively connected to a pair of connection parts each connecting the first or third insulated gate transistor and the second insulated gate transistor; pairs of digit lines each pair of which is connected commonly to the other ends of said first and second select transistors of the unit memory cells arranged in a column direction of the memory array; and word lines connected commonly to the gates of the first and second select transistors of unit memory cells arranged in a row direction of the memory array.

Claim 11

A memory circuit comprising: a memory array having unit memory cells arranged in a matrix fashion, said each unit memory cell having a bistable circuit including a couple of series circuits each memory cells each having a bistable circuit including a couple of series circuits each connected in such a way that first and second insulated gate transistors of the first channel type and a third insulated gate transistor of the second channel type are connected in series fashion, a common connection part is provided commonly connecting the gates of the first and third insulated gate transistors, a control signal is applied to the gate of the second insulated gate transistor through a control signal line separate from said common connection part, and an output part is provided which is a connection part connecting the first or third insulating gate transistor and the second insulated gate transistor, the connection part of one of the series circuit being connected to the output part of the other series circuit while the output part of the former, to the connection part of the latter, a non-volatile memory element connected to the connection part of the first and second insulated gate transistors of one of the series circuits, and first and second select transistors respectively connected to a pair of connection parts each connecting the first or third insulated gate transistor and the second insulated gate transistor; pairs of digit lines each pair of which is connected commonly to the other ends of said first and second select transistors of the unit memory cells arranged in a column direction of the memory array; and word lines connected commonly to the gates of the first and second select transistors of unit memory cells arranged in a row direction of the memory array.

Claim 12

A memory circuit according to claim 9, in which said non-volatile memory element is a MNOS type device.

Claim 13

A memory circuit according to claim 9, in which said non-volatile memory element is a MAOS type device.

Claim 14

A memory array according to claim 9, in which said non-volatile memory element is a floating gate type device.

Claim 15

A memory circuit according to claim 9, in which said first channel is of N-type and said second channel is of P-type.

Claim 16

A memory circuit according to claim 9, in which said first channel is of P-type and said second channel is of N-type.

Claim 17

A memory circuit according to claim 9, wherein the gate electrode of said non-volatile memory element is connected to a non-volatile memory control signal line, separate from said common connection part and said control signal line.

Claim 18

A memory circuit according to claim 9, wherein the voltage applied to said series circuits is less than the voltage applied to the non-volatile memory element.

Claim 19

A memory circuit having a power source, a bistable circuit connected to the power source, a non-volatile memory element connected to the bistable circuit, a control signal line for supplying a control signal to the bistable circuit, and a non-volatile memory control line for supplying a control signal to the non-volatile memory element, in which said bistable circuit comprising: a pair of first insulated gate transistors having first, second and third terminals; a pair of second insulated gate transistors of the same channel type as that of said first insulated gate transistor, of which the first terminals are connected in series to the second terminals of the first insulated gate transistors and the third terminals are connected to said control signal line: a pair of third insulated gate transistors of the channel type different from that of said first and second insulated gate transistors, of which the second terminals are connected to the second terminals of said second transistors and the first terminals are connected to said power source, wherein said control signal line is separate from the connection of the first terminal of the second insulated gate transistor with the second terminal of the first insulated gate transistor, and wherein a first connection point between said first insulated gate transistor and said second insulated gate transistor in one of said series circuits is connected to a connecting point between the gate of said first insulated gate transistor and the gate of said third insulated gate transistor in the other series circuit, the first terminal of at least one non-volatile memory element is connected to said first connection point.

Claim 20

A memory circuit having a power source, a bistable circuit connected to the power source, a non-volatile memory element connected to the bistable circuit, a control signal line for supplying a control signal to the bistable circuit, and a non-volatile memory control line for supplying a control signal to the non-volatile memory element, in which said bistable circuit comprising: a pair of first insulated gate transistors having first, second and third terminals; a pair of second insulated gate transistors of the same channel type as that of said first insulated gate transistor, of which the first terminals are connected in series to the second terminals of the first insulated gate transistors and the third terminals are connected to said control signal line: a pair of third insulated gate transistors of the channel type different from that of said first and second insulated gate transistors, of which the second terminals are connected to the second terminals of said second transistors and the first terminals are connected to said power source, wherein said control signal line is separate from the connection of the first terminal of the second insulated gate transistor with the second terminal of the first insulated gate transistor, and wherein a first connection point between said first insulated gate transistor and said second insulated gate transistor in one of said series circuits is connected to a connecting point between the gate of said first insulated gate transistor and the gate of said third insulated gate transistor in the other series circuit, the first terminal of at least one non-volatile memory element is connected to said first connection point.

Claim 21

A memory circuit according to claim 17, in which said first channel is a N-channel and said second channel is a P-channel.

Claim 22

A memory circuit according to claim 18, in which said first, said second and said third terminals are a source, a drain and a gate, respectively.

Claim 23

A memory circuit according to claim 17, in which said first channel is of the P-type, and said second channel is of the N-type.

Claim 24

A memory circuit according to claim 20, in which said first, said second, and said third terminals are a drain, a source and a gate, respectively.

Claim 25

A memory circuit according to claim 17, in which said non-volatile memory element is a MNOS type device.

Claim 26

A memory circuit according to claim 17, in which said non-volatile memory element is a MAOS type device.

Claim 27

A memory circuit according to claim 17, in which said non-volatile memory element is a floating gate type device.

Claim 28

A memory circuit according to claim 17, wherein the gate electrode of said non-volatile memory element is connected to said non-volatile memory control line, separate from said control signal line.

Claim 29

A memory circuit according to claim 17, wherein the voltage applied to said series circuits is less than the voltage applied to the non-volatile memory element.