US5239503A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High voltage random-access memory cell incorporating level shifter
Assignee: Mentor Graphics Corp
•
Filing: 1992-06-17
•
Granted: 1993-08-24
•
Expires: 2012-06-17
Abstract
Abstract A level-shifting static random access memory cell includes a first stage having a first P-Channel MOS transistor having its source connected to a high voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The source of the first N-Channel MOS transistor is connected to the drain of a second N-Channel MOS transistor. The source of the second N-channel MOS transistor is connected to a VSS power supply rail. A second stage comprises a second P-Channel MOS transistor having its source connected to the high voltage supply rail V HS , and its drain connected to the drain of a third N-Channel MOS transistor. The source of the third N-Channel MOS transistor is connected to the drain of a fourth N-Channel MOS transistor. The source of the fourth N-channel MOS transistor is connected to VSS. The gates of the first and second P-Channel MOS transistors are cross coupled and the gates of the second and fourth N-Channel MOS transistors are cross coupled. The gates of the first and third N-channel MOS transistors are connected together to power supply rail V DD , usually 5 volts. The first and second P-channel MOS transistors are formed in an n-well biased at power supply voltage V HS . A bit line coupled to the drain of the second N-Channel MOS transistor through a fifth N-Channel MOS transistor, having its gate connected to a word line.
Inventors
- 👤 Ta-Pen Guo
- 👤 Adi Srinivasan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:15
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356113; H03K3/356147; H03K3/356156; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
321 words
A level-shifting static random access memory cell which may be coupled to a bit line and a word line operating at a first set high and low of logic-state voltages substantially equal to a first power-supply rail potential and a second power-supply rail potential, respectively, said level-shifting static random access memory cell having at least one output node operating at a second set of high and low logic state voltages substantially equal to a third high-voltage power-supply rail potential and said second power-supply rail potential, respectively, said cell comprising: a first P-Channel MOS transistor having a source connected to said third high-voltage power-supply rail potential, and further having a drain and a gate; a first N-Channel MOS transistor having a drain connected to the drain of said first P-Channel MOS transistor, a gate connected to said first power-supply rail potential, and a source; a second N-Channel MOS transistor having a drain connected to the source of said first N-Channel MOS transistor, a source connected to said second power-supply rail potential, and a gate; a second P-Channel MOS transistor having a source connected to said third high-voltage power-supply rail potential, and further having a drain connected to the gate of said first P-Channel MOS transistor and a gate to the drain of said first P-Channel MOS transistor; a third N-Channel MOS transistor having a drain connected to the drain of said second P-Channel MOS transistor, a gate connected to said first power-supply rail potential, and a source connected to the gate of said second N-Channel MOS transistor; a fourth N-Channel MOS transistor having a drain connected to the source of said third N-Channel MOS transistor, a source connected to said second power-supply rail potential, and a gate connected to the source of said first N-Channel MOS transistor; wherein said first and second P-Channel MOS transistors are fabricated in an n-well, said n-well being biased at said third high-voltage power supply rail potential.
Claim 2
Dependent Claim
321 words
A level-shifting static random access memory cell which may be coupled to a bit line and a word line operating at a first set high and low of logic-state voltages substantially equal to a first power-supply rail potential and a second power-supply rail potential, respectively, said level-shifting static random access memory cell having at least one output node operating at a second set of high and low logic state voltages substantially equal to a third high-voltage power-supply rail potential and said second power-supply rail potential, respectively, said cell comprising: a first P-Channel MOS transistor having a source connected to said third high-voltage power-supply rail potential, and further having a drain and a gate; a first N-Channel MOS transistor having a drain connected to the drain of said first P-Channel MOS transistor, a gate connected to said first power-supply rail potential, and a source; a second N-Channel MOS transistor having a drain connected to the source of said first N-Channel MOS transistor, a source connected to said second power-supply rail potential, and a gate; a second P-Channel MOS transistor having a source connected to said third high-voltage power-supply rail potential, and further having a drain connected to the gate of said first P-Channel MOS transistor and a gate to the drain of said first P-Channel MOS transistor; a third N-Channel MOS transistor having a drain connected to the drain of said second P-Channel MOS transistor, a gate connected to said first power-supply rail potential, and a source connected to the gate of said second N-Channel MOS transistor; a fourth N-Channel MOS transistor having a drain connected to the source of said third N-Channel MOS transistor, a source connected to said second power-supply rail potential, and a gate connected to the source of said first N-Channel MOS transistor; wherein said first and second P-Channel MOS transistors are fabricated in an n-well, said n-well being biased at said third high-voltage power supply rail potential.
Claim 3
Dependent Claim
45 words
The level-shifting static random access memory cell of claim 1, further including a fifth N-Channel MOS transistor having a source connected to said bit line, a drain connected to the drain of said second N-Channel MOS transistor and a gate connected to said word line.
Claim 4
Dependent Claim
41 words
The level-shifting static random access memory cell of claim 1 wherein said first power-supply rail potential is about 5 volts, said second power-supply rail potential is about zero volts, and said third power-supply rail potential is between 8 and 20 volts.
References Cited (Backward Citations)
US4287574A
Cited
US4403306A
Cited
US4536859A
Cited
US4541073A
Cited
US4779226A
Cited
US4816706A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-23 | 1997-02-22 | 1997-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-23 | 2001-02-22 | 2001-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-23 | 2005-02-22 | 2005-08-24 | $7700.00 | Window Closed / Lapsed |