US5315545A
Expired / Lapsed
US
⏱️ 0.0 years remaining
High-voltage five-transistor static random access memory cell
Assignee: Mentor Graphics Corp
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Filing: 1993-06-15
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Granted: 1994-05-24
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Expires: 2013-06-15
Abstract
Abstract According to a first aspect of the present invention, a static random access memory cell according to the present invention includes two stages. The first stage has a first P-Channel MOS transistor with its source connected to a high-voltage supply rail, and its drain connected to the drain of a first N-Channel MOS transistor. The source of the first N-Channel MOS transistor is connected to the drain of a second N-Channel MOS transistor. The source of the second N-Channel MOS transistor is connected to a V SS power supply rail. The second stage has a second P-Channel MOS transistor with its source connected to the high-voltage supply rail V HS , and its drain connected to the drain of a third N-Channel MOS transistor. The source of the third N-Channel MOS transistor is connected to the drain of a fourth N-Channel MOS transistor. The source of the fourth N-Channel MOS transistor is connected to V SS . The gates of the first and second P-Channel MOS transistors are cross-coupled and the gates of the second and fourth N-Channel MOS transistors are cross-coupled. The gates of the first and third N-Channel MOS transistors are connected together to power supply rail V DD , usually 5 volts. The first and second P-Channel MOS transistors are formed in an n-well biased at a constant power supply voltage. In a preferred embodiment the constant power supply voltage may be V HS . A bit line coupled to the drain of the second N-Channel MOS transistor through a fifth N-Channel MOS transistor, having its gate connected to a word line.
Inventors
- 👤 Ta-Pan Guo
- 👤 Adi Srinivasan
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-07 21:28
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/353; H03K3/356; H03K3/356104; H03K3/356113; H03K3/356147; H03K3/356156; G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/413; G11C11/417; G11C11/419
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
325 words
A level-shifting static random access memory cell which may be coupled to a bit line and a word line operating at a first set of high and low logic-state voltages substantially equal to a first power-supply rail potential and a second power-supply rail potential, respectively, said level-shifting static random access memory cell having at least one output node operating at a second set of high and low logic-state voltages substantially equal to a third high-voltage power-supply rail potential and said second power-supply rail potential, respectively, said cell comprising: a first P-Channel MOS transistor having a source connected to said third high-voltage power-supply rail potential, and further having a drain and a gate; a first N-Channel MOS transistor having a drain connected to said drain of said first P-Channel MOS transistor, and further having a gate connected to said first power-supply rail potential, and a source; a second N-Channel MOS transistor having a drain connected to said source of said first N-Channel MOS transistor, and further having a source connected to said second power-supply rail potential, and a gate; a second P-Channel MOS transistor having a source connected to said third high-voltage power-supply rail potential, and further having a drain connected to said gate of said first P-Channel MOS transistor and a gate connected to said drain of said first P-Channel MOS transistor; a third N-Channel MOS transistor having a drain connected to said drain of said second P-Channel MOS transistor, and further having a gate connected to said first power-supply rail potential, and a source connected to said gate of said second N-Channel MOS transistor; a fourth N-Channel MOS transistor having a drain connected to said source of said third N-Channel MOS transistor, and further having a source connected to said second power-supply rail potential, and a gate connected to said source of said first N-Channel MOS transistor; and switching means connected to said drain of said second P-Channel MOS transistor for switching a component.
Claim 2
Dependent Claim
325 words
A level-shifting static random access memory cell which may be coupled to a bit line and a word line operating at a first set of high and low logic-state voltages substantially equal to a first power-supply rail potential and a second power-supply rail potential, respectively, said level-shifting static random access memory cell having at least one output node operating at a second set of high and low logic-state voltages substantially equal to a third high-voltage power-supply rail potential and said second power-supply rail potential, respectively, said cell comprising: a first P-Channel MOS transistor having a source connected to said third high-voltage power-supply rail potential, and further having a drain and a gate; a first N-Channel MOS transistor having a drain connected to said drain of said first P-Channel MOS transistor, and further having a gate connected to said first power-supply rail potential, and a source; a second N-Channel MOS transistor having a drain connected to said source of said first N-Channel MOS transistor, and further having a source connected to said second power-supply rail potential, and a gate; a second P-Channel MOS transistor having a source connected to said third high-voltage power-supply rail potential, and further having a drain connected to said gate of said first P-Channel MOS transistor and a gate connected to said drain of said first P-Channel MOS transistor; a third N-Channel MOS transistor having a drain connected to said drain of said second P-Channel MOS transistor, and further having a gate connected to said first power-supply rail potential, and a source connected to said gate of said second N-Channel MOS transistor; a fourth N-Channel MOS transistor having a drain connected to said source of said third N-Channel MOS transistor, and further having a source connected to said second power-supply rail potential, and a gate connected to said source of said first N-Channel MOS transistor; and switching means connected to said drain of said second P-Channel MOS transistor for switching a component.
Claim 3
Dependent Claim
31 words
The level-shifting static random access memory cell of claim 1 wherein said switching means is a switching transistor having its gate connected to said drain of said second P-Channel MOS transistor.
Claim 4
Dependent Claim
19 words
The level-shifting static random access memory cell of claim 2 wherein said switching transistor is an N-Channel MOS transistor.
Claim 5
Dependent Claim
34 words
The level-shifting static random access memory cell of claim 3 wherein said first and second P-Channel MOS transistors are fabricated in an n-well, said n-well being biased at said third high-voltage power-supply rail potential.
Claim 6
Dependent Claim
45 words
The level-shifting static random access memory cell of claim 4, further including a fifth N-Channel MOS transistor having a source connected to the bit line, a drain connected to said drain of said second N-Channel MOS transistor, and a gate connected to the word line.
Claim 7
Dependent Claim
42 words
The level-shifting static random access memory cell of claim 5 wherein said first power-supply rail potential is about 5 volts, said second power-supply rail potential is about zero volts, and said third high-voltage power-supply rail potential is between 8 and 20 volts.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1997-05-23 | 1997-11-22 | 1998-05-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2001-05-23 | 2001-11-22 | 2002-05-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2005-05-23 | 2005-11-22 | 2006-05-24 | $7700.00 | Window Closed / Lapsed |