Semiconductor memory device usable as static type memory and read-only memory and operating method therefor

Claim 2

A semiconductor memory device, comprising: a first potential line for receiving a first potential; a second potential line for receiving a second potential; a third potential line for selectively receiving the first potential or the second potential; a fourth potential line for selectively receiving the first potential or the second potential; and at least one memory cell; said memory cell including: a first node and a second node provided with potentials which are complementary to each other; first pull-up/pull-down means connected between either of said first and third potential lines and said first node; second pull-up/pull-down means connected between either of said first and third potential lines and said second node, third pull-up/pull-down means connected between either of said second and fourth potential lines and said first node; and fourth pull-up/pull-down means connected between either of said second and fourth potential lines and said second node.

Claim 3

The semiconductor memory device according to claim 1, wherein said first pull-up/pull-down means includes first conductive channel transistor means having a gate connected to said second node; said second pull-up/pull-down means includes first conductive channel transistor means having a gate connected to said first node; said third pull-up/pull-down means includes second conductive channel transistor means having a gate connected to said second node; and said fourth pull-up/pull-down means includes second conductive channel transistor means having a gate connected to said first node.

Claim 4

The semiconductor memory device according to claim 2, wherein said first conductive channel transistor means includes a P channel MOS transistor; and said second conductive channel transistor means includes a N channel MOS transistor.

Claim 5

The semiconductor memory device according to claim 1, wherein said first pull-up/pull-down means includes high resistance means; said second pull-up/pull-down means includes high resistance means; said third pull-up/pull-down means includes transistor means having a gate connected to said second node; said fourth pull-up/pull-down means includes transistor means having a gate connected to said first node.

Claim 6

The semiconductor memory device according to claim 4, wherein said high resistance means is formed of high resistance polysilicon; and said transistor means includes a N channel MOS transistor.

Claim 7

The semiconductor memory device according to claim 1, wherein said first pull-up/pull-down means includes first depletion type transistor means having a gate connected to said first node; said second pull-up/pull-down means includes second depletion type transistor means having a gate connected to said second node; said third pull-up/pull-down means includes third transistor means having a gate connected to said second node; and said fourth pull-up/pull-down means includes fourth transistor means having a gate connected to said first node.

Claim 8

The semiconductor memory device according to claim 6, wherein each of said first and second depletion type transistor means includes a depletion type N channel MOS transistor; and each of said third and fourth transistor means includes a N channel MOS transistor.

Claim 9

The semiconductor memory device according to claim 1, wherein said first pull-up/pull-down means includes first enhancement type transistor means having a gate connected to either of said first and third potential lines; said second pull-up/pull-down means includes second enhancement type transistor means having a gate connected to either of said first and third potential lines; said third pull-up/pull-down means includes third transistor means having a gate connected to said second node; said fourth pull-up/pull-down means includes fourth transistor means having a gate connected to said first node.

Claim 10

The semiconductor memory device according to claim 8, wherein each of said first and second enhancement type transistor means includes an enhancement type N channel MOS transistor; and each of said third and fourth transistor means includes a N channel MOS transistor.

Claim 11

The semiconductor memory device according to claim 1, wherein said first pull-up/pull-down means includes first TFT type first conductive channel transistor means having a gate connected to said second node; said second pull-up/pull-down means includes second TFT type first conductive channel transistor means having a gate connected to said first node; said third pull-up/pull-down means includes second conductive channel transistor means having a gate connected to said second node; and said fourth pull-up/pull-down means includes second conductive channel MOS transistor means having a gate connected to said first node.

Claim 12

The semiconductor memory device according to claim 10, wherein each of said TFT type first conductive channel transistor means includes a TFT type P channel MOS transistor; and each of said second conductive channel transistor means includes N channel MOS transistor.

Claim 13

The semiconductor memory device according to claim 1, further comprising: a first program means capable of preconnecting each of said first and second pull-up/pull-down means to either of said first and third potential lines; and a second program means capable of preconnecting each of said third and fourth pull-up/pull-down means to either of said second and fourth potential line.

Claim 14

The semiconductor memory device according to claim 12, wherein each of said first and second program means determines the connection state, depending on the presence or absence of a contact.

Claim 15

The semiconductor memory device according to claim 12, wherein each of said first and second program means determines the connection state, depending on the presence or absence of a through hole.

Claim 16

The semiconductor memory device according to claim 12, wherein each of said first and second program means determines the connection state, depending on the presence or absence of a diffusion region.

Claim 17

The semiconductor memory device according to claim 1, wherein said first potential corresponds to the supply potential; said second potential corresponds to the ground potential.

Claim 18

A semiconductor memory device comprising: a plurality of word lines; a plurality of bit line pair each comprising a first bit line and a second bit line and arranged so as to cross said plurality of word lines; a first potential line for receiving a first potential; a second potential line for receiving a second potential; a third potential line for selectively receiving the first potential or the second potential; a fourth potential line for selectively receiving the first potential or the second potential; and a plurality of memory cells provided at the crossings of said plurality of word lines and plurality of bit line pairs each of said plurality of memory cells including; a first node and a second node provided with potentials which are complementary to each other; first pull-up/pull-down means connected between either of said first and third potential lines and said first node; second pull-up/pull-down means connected between either of said first and third potential lines and said second node; third pull-up/pull-down means connected between either of said second and fourth potential lines and said first node; and fourth pull-up/pull-down means connected to either of said second and fourth potential lines and said second node.

Claim 19

A semiconductor memory device comprising: a plurality of word lines; a plurality of bit line pair each comprising a first bit line and a second bit line and arranged so as to cross said plurality of word lines; a first potential line for receiving a first potential; a second potential line for receiving a second potential; a third potential line for selectively receiving the first potential or the second potential; a fourth potential line for selectively receiving the first potential or the second potential; and a plurality of memory cells provided at the crossings of said plurality of word lines and plurality of bit line pairs each of said plurality of memory cells including; a first node and a second node provided with potentials which are complementary to each other; first pull-up/pull-down means connected between either of said first and third potential lines and said first node; second pull-up/pull-down means connected between either of said first and third potential lines and said second node; third pull-up/pull-down means connected between either of said second and fourth potential lines and said first node; and fourth pull-up/pull-down means connected to either of said second and fourth potential lines and said second node.

Claim 22

A semiconductor memory device comprising: at least one memory cell having switching transistors in two circuit portions, each circuit portion including an input node and an output node, each input node connected to the output node of the other circuit portion to define a cross coupling, the two output nodes having complementary digital voltage levels, one of said output nodes forming a memory cell output indicative of stored cell information, each circuit portion further including a first and a second terminal; and voltage applying means for selectively applying a voltage of either a high digital level or low digital level to each of said first and second terminals, whereby said memory cell may operate selectively as a SRAM cell, a ROM cell having a high digital level storage or as a ROM cell having a low digital level storage.

Claim 23

A semiconductor memory device comprising: at least one memory cell having switching transistors in two circuit portions, each circuit portion including an input node and an output node, each input node connected to the output node of the other circuit portion to define a cross coupling, the two output nodes having complementary digital voltage levels, one of said output nodes forming a memory cell output indicative of stored cell information, each circuit portion further including a first and a second terminal; and voltage applying means for selectively applying a voltage of either a high digital level or low digital level to each of said first and second terminals, whereby said memory cell may operate selectively as a SRAM cell, a ROM cell having a high digital level storage or as a ROM cell having a low digital level storage.

Claim 24

A semiconductor memory device comprising: at least one memory cell having switching transistors in two circuit portions, each circuit portion including an input node and an output node, each input node connected to the output node of the other circuit portion to define a cross coupling, the two output nodes having complementary digital voltage levels, one of said output nodes forming a memory cell output indicative of stored cell information, each circuit portion further including a first and a second terminal; and voltage applying means for selectively applying a voltage of either a high digital level or a low digital level to each of said first and second terminals, whereby said memory cell may operate selectively as a SRAM cell, a ROM cell having a high digital level storage or as a ROM cell having a low digital level storage, wherein said voltage applying means comprises: a high voltage level reference source, a low voltage level reference source; and four conductive lines respectively connected to the first and second terminals of the two circuit portions, a first one of said conductive lines being supplied with said high voltage level reference source, a second one of said conductive lines being supplied with said low voltage level reference source, and the remaining conductive lines being independently selectively supplied with one of said high and low voltage level reference sources.

Claim 25

A semiconductor memory device comprising: at least one memory cell having switching transistors in two circuit portions, each circuit portion including an input node and an output node, each input node connected to the output node of the other circuit portion to define a cross coupling, the two output nodes having complementary digital voltage levels, one of said output nodes forming a memory cell output indicative of stored cell information, each circuit portion further including a first and a second terminal; and voltage applying means for selectively applying a voltage of either a high digital level or a low digital level to each of said first and second terminals, whereby said memory cell may operate selectively as a SRAM cell, a ROM cell having a high digital level storage or as a ROM cell having a low digital level storage, wherein said voltage applying means comprises: a high voltage level reference source, a low voltage level reference source; and four conductive lines respectively connected to the first and second terminals of the two circuit portions, a first one of said conductive lines being supplied with said high voltage level reference source, a second one of said conductive lines being supplied with said low voltage level reference source, and the remaining conductive lines being independently selectively supplied with one of said high and low voltage level reference sources.

Claim 26

A semiconductor memory device as recited in claim 20, wherein said first terminals in said two circuit portions are connected to said first one of said conductive lines, one of said second terminals in said two circuit portions is connected to one of said remaining conductive lines, and the other of said second terminals in said two circuit portions is connected to said second one of said conductive lines.

Claim 27

A semiconductor memory device as recited in claim 20, wherein one of said first terminals in said two circuit portions is connected to one of said remaining conductive lines, the other of said first terminals in said two circuit portions is connected to said first one of said conductive lines, and said second terminals in said two circuit portions are connected to said second one of said conductive lines.

Claim 28

A semiconductor memory device as recited in claim 20, wherein one of said first terminals in said two circuit portions is connected to a first one of said remaining conductive lines having voltage selectively applied thereto and one of said second terminals of said two circuit portions is connected to a second one of said remaining conductive lines having voltage applied thereto.

Claim 29

A semiconductor memory device comprising: a plurality of memory cells arranged in an array of rows and columns, each memory cell having switching transistors in two circuit portions, each circuit portion including an input node and an output node, each input node connected to the output node of the other circuit portion to define a cross coupling, the two output nodes having complementary digital voltage levels, one of said output nodes forming a memory cell output indicative of stored cell information, each circuit portion further including a first and a second terminal; a plurality of parallel conductive lines extending along each column, the first and second terminals of said two circuit portions of each memory cell in each column connected to individual ones of said conductive lines corresponding thereto; and voltage applying means for selectively applying a voltage of either a high digital level or a low digital level to at least two of said conductive lines corresponding to each column, whereby said memory cells may operate selectively as SRAM cells, ROM cells having a high digital level storage or as ROM cells having a low digital level storage.

Claim 30

A semiconductor memory device comprising: a plurality of memory cells arranged in an array of rows and columns, each memory cell having switching transistors in two circuit portions, each circuit portion including an input node and an output node, each input node connected to the output node of the other circuit portion to define a cross coupling, the two output nodes having complementary digital voltage levels, one of said output nodes forming a memory cell output indicative of stored cell information, each circuit portion further including a first and a second terminal; a plurality of parallel conductive lines extending along each column, the first and second terminals of said two circuit portions of each memory cell in each column connected to individual ones of said conductive lines corresponding thereto; and voltage applying means for selectively applying a voltage of either a high digital level or a low digital level to at least two of said conductive lines corresponding to each column, whereby said memory cells may operate selectively as SRAM cells, ROM cells having a high digital level storage or as ROM cells having a low digital level storage.

Claim 31

A semiconductor memory device comprising: a plurality of word lines and a plurality of bit lines crossing said plurality of word lines; a plurality of memory cells arranged in an array of rows and columns at crossing points of said plurality of word lines and said plurality of bit lines, each memory cell having switching transistors forming a latch circuit; a plurality of parallel conductive lines extending along each column, crossing said plurality of word lines, for selecting connection to the memory cells in the respective column; and voltage applying means for selectively applying a voltage of either high digital level or low digital level to at least two of said plurality of conductive lines corresponding to each columns, whereby said memory cells may operate selectively as SRAM cells, ROM cells having a high digital level storage or as ROM cells having a low digital level storage.

Claim 32

A semiconductor memory device comprising: a plurality of word lines and a plurality of bit lines crossing said plurality of word lines; a plurality of memory cells arranged in an array of rows and columns at crossing points of said plurality of word lines and said plurality of bit lines, each memory cell having switching transistors forming a latch circuit; a plurality of parallel conductive lines extending along each column, crossing said plurality of word lines, for selecting connection to the memory cells in the respective column; and voltage applying means for selectively applying a voltage of either high digital level or low digital level to at least two of said plurality of conductive lines corresponding to each columns, whereby said memory cells may operate selectively as SRAM cells, ROM cells having a high digital level storage or as ROM cells having a low digital level storage.

Claim 33

A semiconductor memory device comprising: a plurality of word lines and a plurality of bit lines crossing said plurality of word lines; a plurality of memory cells arranged in an array of rows and columns, each memory cell having an array of rows and columns, each memory cell having switching transistors forming a latch circuit; a plurality of parallel conductive lines arranged for every two columns, crossing said plurality of word lines, and for selective connection to the memory cells in the respective adjacent two columns; and voltage applying means for selectively applying a voltage of either high digital level or low digital level to at least two of said plurality of parallel conductive lines corresponding to each columns, whereby said memory cells may operate selectively as SRAM cells, ROM cells having a high digital level storage or as ROM cells having a low digital level storage.

Claim 34

A semiconductor memory device comprising: a plurality of word lines and a plurality of bit lines crossing said plurality of word lines; a plurality of memory cells arranged in an array of rows and columns, each memory cell having an array of rows and columns, each memory cell having switching transistors forming a latch circuit; a plurality of parallel conductive lines arranged for every two columns, crossing said plurality of word lines, and for selective connection to the memory cells in the respective adjacent two columns; and voltage applying means for selectively applying a voltage of either high digital level or low digital level to at least two of said plurality of parallel conductive lines corresponding to each columns, whereby said memory cells may operate selectively as SRAM cells, ROM cells having a high digital level storage or as ROM cells having a low digital level storage.

Claim 35

A semiconductor memory device comprising: at least one memory cell, first line supplied with a voltage of low digital level, second line selectively supplied with one of voltages of high and low digital levels, third lines supplied with a voltage of high digital level, and fourth line selectively supplied with one of voltages of high and low digital levels, said memory cell comprising first and second storage nodes, a first MOS transistor connected between said first storage node and selected one of said first and second lines and having a gate electrode connected to said second storage node, a second MOS transistor connected between said second storage node and selected one of said first and second lines and having a gate electrode connected to said first storage node, a first element having a first node connected to selected one of said third and fourth lines and a second node connected to said first storage node, and a second element having a first node connected to selected one of said third and fourth lines and a second node connected to said second storage node.

Claim 36

A semiconductor memory device comprising: at least one memory cell, first line supplied with a voltage of low digital level, second line selectively supplied with one of voltages of high and low digital levels, third lines supplied with a voltage of high digital level, and fourth line selectively supplied with one of voltages of high and low digital levels, said memory cell comprising first and second storage nodes, a first MOS transistor connected between said first storage node and selected one of said first and second lines and having a gate electrode connected to said second storage node, a second MOS transistor connected between said second storage node and selected one of said first and second lines and having a gate electrode connected to said first storage node, a first element having a first node connected to selected one of said third and fourth lines and a second node connected to said first storage node, and a second element having a first node connected to selected one of said third and fourth lines and a second node connected to said second storage node.