US5204990A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory cell with capacitance for single event upset protection
Assignee: Texas Instruments Inc
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Filing: 1988-09-07
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Granted: 1993-04-20
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Expires: 2008-09-07
Abstract
Abstract A compact capacitor for use in a small memory cell in high density memories is disclosed. Such a capacitor in the cross-coupling of cross-coupled inverters in the memory cell improves single event upset hardness. The subject capacitor in its preferred embodiment is a MOS capacitor with both n+ and p+ connections to the capacitor channel so as to maintain a relatively high capacitance for both positive and negative capacitor gate voltages.
Inventors
- 👤 Terence G. W. Blake
- 👤 Theodore W. Houston
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 06:13
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/005; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/4125; H; H10; H10B; H10B10/00; H10B10/12; Y; Y10; Y10S; Y10S257/00; Y10S257/903; Y10S257/904
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
56 words
A memory cell including a pair of cross-coupled inverters and further including a MOS capacitor connected across the cross-couplings of said pair of inverters, said MOS capacitor including a gate region, a channel region and a source region comprising both heavily doped n-type semiconductor material and heavily doped p-type semiconductor material connected to said channel region.
Claim 2
Dependent Claim
56 words
A memory cell including a pair of cross-coupled inverters and further including a MOS capacitor connected across the cross-couplings of said pair of inverters, said MOS capacitor including a gate region, a channel region and a source region comprising both heavily doped n-type semiconductor material and heavily doped p-type semiconductor material connected to said channel region.
Claim 3
Dependent Claim
27 words
A memory cell as recited in claim 1 wherein said heavily doped n and p type semiconductor material of said MOS capacitor lie adjacent to one another.
Claim 4
Dependent Claim
24 words
A memory cell as recited in claim 1 wherein said adjacent heavily doped n and p type semiconductor material are connected together with silicide.
Claim 5
Dependent Claim
64 words
A memory cell as recited in claim 1 in which said gate region comprises a polycrystalline semiconductor region and said channel region comprises a lightly doped p-type semiconductor material and wherein said heavily doped n-type semiconductor material lies adjacent said heavily doped p-type semiconductor material and wherein said MOS capacitor further includes a gate oxide layer lying over said lightly doped p-type channel region.
Claim 6
Dependent Claim
17 words
A memory cell as recited in claim 4 wherein said adjacent semiconductor materials are connected by silicide.
Claim 7
Dependent Claim
64 words
A memory cell as recited in claim 1 in which said gate region comprises a polycrystalline semiconductor region and said channel region comprises a lightly doped n-type semiconductor material and wherein said heavily doped n-type semiconductor material lies adjacent said heavily doped p-type semiconductor material and wherein said MOS capacitor further includes a gate oxide layer lying over said lightly doped n-type channel region.
Claim 8
Dependent Claim
17 words
A memory cell as recited in claim 6 wherein said adjacent semiconductor materials are connected by silicide.
Claim 9
Dependent Claim
14 words
A memory cell as recited in claim 1 wherein said semiconductor material is silicon.
Claim 10
Dependent Claim
15 words
A memory cell as recited in claim 1 wherein said semiconductor material is gallium arsenide.
Claim 11
Dependent Claim
18 words
A memory cell as recited in claim 1 wherein said inverters include at least one field effect transistor.
Claim 12
Dependent Claim
40 words
A layout for the memory cell as recited in claim 10 wherein said MOS capacitor is formed by the extension of the gate of said at least one field effect transistor over the drain of said at least one transistor.
Claim 13
Dependent Claim
30 words
A layout for the memory cell as recited in claim 10 wherein said gate region of said MOS capacitor extends substantially along at least one dimension of said memory cell.
References Cited (Backward Citations)
GB1163788A
Cited
US4827448A
Cited
US4481524A
Cited
US4453175A
Cited
JPS5683073A
Cited
US4614881A
Cited
US4745454A
Cited
JPS61208698A
Cited
US4725981A
Cited
US4833644A
Cited
US4912675A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-04-19 | 1996-10-19 | 1997-04-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-04-19 | 2000-10-19 | 2001-04-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-04-19 | 2004-10-19 | 2005-04-20 | $7700.00 | Window Closed / Lapsed |