US4725981A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Random access memory cell resistant to inadvertant change of state due to charged particles
Assignee: Motorola Solutions Inc
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Filing: 1986-02-03
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Granted: 1988-02-16
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Expires: 2006-02-03
Abstract
Abstract A static MOS RAM cell is provided that is resistant to inadvertent change of state due to charged particles striking the cell without decreasing write time. First and second cross-coupled transistors are coupled between first and second nodes, respectively, and a first voltage. First and second loads are coupled between the first and second nodes, respectively, and a second voltage. A first coupling transistor is coupled between the first node and a first input terminal, and has a gate coupled for receiving a write signal. A second coupling transistor is coupled between the second node and a second input terminal, and has a gate coupled for receiving the write signal. First and second variable loads are coupled between the first node and a gate of the second latching transistor, and the second node and a gate of the first latching transistor, respectively, for providing a resistance in the standby mode and relatively no resistance in the write mode.
Inventors
- 👤 James L. Rutledge
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 11:39
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/4125
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
203 words
A memory cell having a first data line, a second data line, a first input terminal and a second input terminal, said memory cell comprising: a pair of cross-coupled transistors coupled between first and second nodes, respectively, and a first voltage; first means coupled between said first node and a second voltage for providing a resistance; second means coupled between said second node and said second voltage for providing a resistance; third means coupled between said first node and said first input terminal and coupled for receiving a write signal for coupling a first input signal to said first node; fourth means coupled between said second node and said second input terminal and coupled for receiving a write signal for coupling a second input signal to said second node; fifth means coupled for receiving said write signal and coupled between said first node and the gate of one of said pair of cross-coupled transistors for varying the resistance therebetween in response to said write signal; and sixth means coupled for receiving said write signal and coupled between said second node and the gate of the other of said pair of cross-coupled transistors for varying the resistance therebetween in response to said write signal.
Claim 2
Dependent Claim
203 words
A memory cell having a first data line, a second data line, a first input terminal and a second input terminal, said memory cell comprising: a pair of cross-coupled transistors coupled between first and second nodes, respectively, and a first voltage; first means coupled between said first node and a second voltage for providing a resistance; second means coupled between said second node and said second voltage for providing a resistance; third means coupled between said first node and said first input terminal and coupled for receiving a write signal for coupling a first input signal to said first node; fourth means coupled between said second node and said second input terminal and coupled for receiving a write signal for coupling a second input signal to said second node; fifth means coupled for receiving said write signal and coupled between said first node and the gate of one of said pair of cross-coupled transistors for varying the resistance therebetween in response to said write signal; and sixth means coupled for receiving said write signal and coupled between said second node and the gate of the other of said pair of cross-coupled transistors for varying the resistance therebetween in response to said write signal.
Claim 3
Dependent Claim
57 words
The memory cell according to claim 1 wherein said fifth and sixth means respectively comprise a first and second depletion device wherein a substantially small amount of current would flow therethrough when said write signal is in one state and a substantially larger amount of current would flow therethrough when said write signal is in another state.
Claim 4
Dependent Claim
51 words
The memory cell according to claim 1 wherein said fifth and sixth means respectively comprise a first resistor and a first bypass transistor in parallel and a second resistor and a second bypass transistor in parallel, said first and second bypass transistors having a gate coupled for receiving said write signal.
Claim 5
Dependent Claim
20 words
The memory cell according to claim 3 wherein said first and second means respectively comprise a third and fourth resistor.
Claim 6
Dependent Claim
39 words
The memory cell according to claim 3 wherein said first and second means respectively comprise a first and second load transistor having a gate coupled to said second and first node, respectively, by said sixth and fifth means, respectively.
Claim 7
Dependent Claim
30 words
The memory cell according to claim 3 wherein said third and fourth means respectively comprise a first and second coupling transistor having a gate coupled for receiving said write signal.
Claim 8
Dependent Claim
183 words
A memory cell having a first data line, a second data line, and a word line, said memory cell comprising: a first latching transistor coupled between a first voltage and a first node; a second latching transistor coupled between said first voltage and a second node; a first load coupled between said first node and a second voltage; a second load coupled between said second node and said second voltage; a first coupling transistor coupled between said first node and a first input signal, and having a gate coupled for receiving a write signal; a second coupling transistor coupled between said second node and a second input signal, and having a gate coupled for receiving said write signal; first means coupled for receiving said write signal and between said first node and a gate of said second latching transistor for varying the resistance therebetween in response to said write signal; and second means coupled for receiving said write signal and between said second node and a gate of said first latching transistor for varying the resistance therebetween in response to said write signal.
Claim 9
Dependent Claim
183 words
A memory cell having a first data line, a second data line, and a word line, said memory cell comprising: a first latching transistor coupled between a first voltage and a first node; a second latching transistor coupled between said first voltage and a second node; a first load coupled between said first node and a second voltage; a second load coupled between said second node and said second voltage; a first coupling transistor coupled between said first node and a first input signal, and having a gate coupled for receiving a write signal; a second coupling transistor coupled between said second node and a second input signal, and having a gate coupled for receiving said write signal; first means coupled for receiving said write signal and between said first node and a gate of said second latching transistor for varying the resistance therebetween in response to said write signal; and second means coupled for receiving said write signal and between said second node and a gate of said first latching transistor for varying the resistance therebetween in response to said write signal.
Claim 10
Dependent Claim
57 words
The memory cell according to claim 7 wherein said first and second means respectively comprise a first and second depletion device wherein a substantially small amount of current would flow therethrough when said write signal is in one state and a substantially larger amount of current would flow therethrough when said write signal is in another state.
Claim 11
Dependent Claim
51 words
The memory cell according to claim 7 wherein said first and second means respectively comprise a first resistor and a first bypass transistor in parallel and a second resistor and a second bypass transistor in parallel, said first and second bypass transistors having a gate coupled for receiving said write signal.
Claim 12
Dependent Claim
37 words
The memory cell according to claim 9 wherein said first and second loads respectively comprise a first and second load transistor, each having a gate coupled to the gate of said first and second latching transistors, respectfully.
Claim 13
Dependent Claim
20 words
The memory cell according to claim 9 wherein said first and second loads respectively comprise a first and second resistor.
References Cited (Backward Citations)
US4130892A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
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| 3.5 Years (Year 4) | 1991-02-15 | 1991-08-17 | 1992-02-16 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-02-15 | 1995-08-17 | 1996-02-16 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-02-15 | 1999-08-17 | 2000-02-16 | $7700.00 | Window Closed / Lapsed |