US4833644A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Memory cell circuit having radiation hardness
Assignee: Intersil Corp
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Filing: 1986-08-26
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Granted: 1989-05-23
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Expires: 2006-08-26
Abstract
Abstract A memory cell circuit has a pair of inverters and a means, such as gate-drain coupled capacitors, for providing a greater voltage difference at MOS transistor gates during radiation than an initial value. This tends to preserve the latch logic state and thus prevent a change in logic state during radiation.
Inventors
- 👤 Dora Plus
- 👤 Roger G. Stewart
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-06 06:09
CPC Classifications
G; G11; G11C; G11C5/00; G11C5/005; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/412; G11C11/4125; H; H10; H10B; H10B10/00; H10B10/12
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
115 words
A memory cell circuit comprising: first and second cross-coupled inverters, each inverter having first and second complementary MOS series coupled transistors, each of said transistors having a pair of conduction electrodes and a gate input electrode, one of said conduction electrodes being an output electrode coupled to the output electrode of the respective complementary transistor; and a first capacitor coupled between said gate input electrodes of said first and second transistors of said first inverter, and the conduction output electrodes of said first inverter transistors, and a second capacitor coupled between said gate input electrodes of said first and second transistors of said second inverter, and the conduction output electrodes of said second inverter transistors.
Claim 2
Dependent Claim
115 words
A memory cell circuit comprising: first and second cross-coupled inverters, each inverter having first and second complementary MOS series coupled transistors, each of said transistors having a pair of conduction electrodes and a gate input electrode, one of said conduction electrodes being an output electrode coupled to the output electrode of the respective complementary transistor; and a first capacitor coupled between said gate input electrodes of said first and second transistors of said first inverter, and the conduction output electrodes of said first inverter transistors, and a second capacitor coupled between said gate input electrodes of said first and second transistors of said second inverter, and the conduction output electrodes of said second inverter transistors.
Claim 3
Dependent Claim
13 words
The cell of claim 1 wherein said capacitors have about equal capacitance values.
Claim 4
Dependent Claim
14 words
The cell of claim 2 wherein said capacitors have about the same physical size.
Claim 5
Dependent Claim
58 words
The cell of claim 1 further comprising a first resistor coupled between said gate electrodes of said first inverter transistors and a conduction electrode of said second transistor of said second inverter, and a second resistor coupled between said gate electrodes of said second inverter transistors and a conduction electrode of said second transistor of said first inverter.
Claim 6
Dependent Claim
25 words
The cell of claim 4 wherein said capacitors comprise a lower plate and an upper plate lying substantially within the periphery of said lower plate.
Claim 7
Dependent Claim
13 words
The cell of claim 4 wherein said resistors have about equal resistance values.
Claim 8
Dependent Claim
25 words
The cell of claim 1 wherein said each of said capacitors comprise upper and lower plates coupled to said gate and conduction output electrodes, respectively.
Claim 9
Dependent Claim
41 words
The cell of claim 1 wherein said first and second transistors of said first inverter have about the same physical size and structure and said first and second transistors of said second inverter have about the same physical size and structure.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-05-22 | 1992-11-21 | 1993-05-23 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-05-22 | 1996-11-21 | 1997-05-23 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-05-22 | 2000-11-21 | 2001-05-23 | $7700.00 | Window Closed / Lapsed |