US4314359A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Semiconductor memory device
Assignee: Hitachi Ltd
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Filing: 1980-06-06
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Granted: 1982-02-02
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Expires: 2000-06-06
Abstract
Abstract The invention relates to an improvement in a semiconductor memory device including flip-flop type memory cells, each memory cell consisting of a pair of cross-coupled multi-emitter transistors. The semiconductor memory device of the invention is characterized by including a capacitance added between the collector region and the base region of each of the transistor pair of each memory cell in order to prevent the memory cell from erroneously operating due to α-rays.
Inventors
- 👤 Yukio Kato
- 👤 Atsuo Hotta
- 👤 Teruo Isobe
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:14
CPC Classifications
G; G11; G11C; G11C11/00; G11C11/21; G11C11/34; G11C11/40; G11C11/41; G11C11/413; G11C11/414; G11C11/411; G11C11/4116; H; H10; H10B; H10B10/00; H10B10/10; H10D; H10D84/00; H10D84/60; H10D84/611; H10D84/613; Y; Y10; Y10S; Y10S438/00; Y10S438/901
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
163 words
In a semiconductor memory device comprising: a matrix of memory cells arranged in rows and columns; each of said memory cells including a pair of multi-emitter transistors; each of said pair of multi-emitter transistors having two emitters, a collector and a base; the base and collector of one of said pair of multi-emitter transistors cross-coupled to those of the other; one each of the emitters of said pair of multi-emitter transistors connected commonly to a current source; the other each of the emitters of said pair of multi-emitter transistors connected to a pair of column lines, respectively; the collectors of said pair of multi-emitter transistors connected to row lines via load means, respectively; and a peripheral circuit consisting of plural transistors each having an emitter, collector and base, and connected to said row and column lines; the improvement wherein capacitance means are added to said pair of multi-emitter transistors of each of said memory cells, respectively in order to increase the collector-to-base capacitance.
Claim 2
Dependent Claim
163 words
In a semiconductor memory device comprising: a matrix of memory cells arranged in rows and columns; each of said memory cells including a pair of multi-emitter transistors; each of said pair of multi-emitter transistors having two emitters, a collector and a base; the base and collector of one of said pair of multi-emitter transistors cross-coupled to those of the other; one each of the emitters of said pair of multi-emitter transistors connected commonly to a current source; the other each of the emitters of said pair of multi-emitter transistors connected to a pair of column lines, respectively; the collectors of said pair of multi-emitter transistors connected to row lines via load means, respectively; and a peripheral circuit consisting of plural transistors each having an emitter, collector and base, and connected to said row and column lines; the improvement wherein capacitance means are added to said pair of multi-emitter transistors of each of said memory cells, respectively in order to increase the collector-to-base capacitance.
Claim 3
Dependent Claim
55 words
The semiconductor memory device as defined in claim 1 wherein said capacitance connected between the collector and base of each of said pair of multi-emitter transistors of each of said memory cells has a value greater than the parasitic capacitance between the collector and base of each of said plural transistors forming said peripheral circuit.
Claim 4
Dependent Claim
129 words
The semiconductor memory device as defined in claim 2 wherein said pair of multi-emitter transistors forming each of said memory cells and said plural transistors forming said peripheral circuit are formed in one semiconductor substrate, the impurity concentrations of the emitter semiconductor and base semiconductor regions are substantially equal to those in the emitter semiconductor and base semiconductor regions of each of said plural transistors of said peripheral circuit, respectively, and the collector semiconductor region of each of said pair of multi-emitter transistors has a high impurity concentration region formed at least a part thereof having an impurity concentration substantially higher than that of the collector seimiconductor region of each of said plural transistors of said peripheral circuit so that high impurity concentration region serves as said capacitance means.
References Cited (Backward Citations)
US3786442A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1985-02-01 | 1985-08-03 | 1986-02-02 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1989-02-01 | 1989-08-03 | 1990-02-02 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1993-02-01 | 1993-08-03 | 1994-02-02 | $7700.00 | Window Closed / Lapsed |